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Commit bf0d9cd2 authored by patacongo's avatar patacongo
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Add Kinetis IRQ numbers 

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3850 42af7a65-404d-4744-a932-0658087f49c3
parent 38009a37
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TODO
+ 20
− 4
View file @ bf0d9cd2
......@@ -14,7 +14,7 @@ nuttx/
(2) USB (drivers/usbdev, drivers/usbhost)
(6) Libraries (lib/)
(10) File system/Generic drivers (fs/, drivers/)
(1) Graphics subystem (graphics/)
(2) Graphics subystem (graphics/)
(1) Pascal add-on (pcode/)
(1) Documentation (Documentation/)
(5) Build system / Toolchains
......@@ -481,6 +481,18 @@ o Graphics subystem (graphics/)
in the current structure.
Priority: Low.
Description: In the kernel build mode (where NuttX is built as a monlithic
kernel and user code must trap into the protected kernel via
syscalls), the single user mode cannot be supported. In this
built configuration, only the multiple user mode can be supported
with the NX server residing inside of the kernel space. In
this case, most of the user end functions in graphics/nxmu
must be moved to lib/nx and those functions must be built into
libuser.a to be linked with the user-space code.
Status: Open
Priority: Low -- the kernel build configuration is not fully fielded
yet.
o Pascal Add-On (pcode/)
^^^^^^^^^^^^^^^^^^^^^^
......@@ -548,7 +560,7 @@ o Build system
1. This script assumes the host archiver ar may not be appropriate for
non-GCC toolchains
2. For the kernel build, the user libriars should be built into some
2. For the kernel build, the user libraries should be built into some
libuser.a. The list of user libraries would have to accepted with
some new argument, perhaps -u.
Status: Open
......@@ -661,9 +673,13 @@ o ARM (arch/arm/)
using 'ldmia sp, {r0-r15}^' My understanding is that this works
fine because everything is in kernel-mode. In an operating model
where applications run in user mode and interrupts/traps run in
kernel-mode, I think that there is a problem with this.
kernel-mode, I think that there is a problem with this. This would
like be a problem, for example, if for a kernel build where NuttX
is built as a monolithic, protected kernel and user mode programs
trap into the kernel.
Status: Open
Priority: Low until I get around to implement security for the ARM platform.
Priority: Low until I get around to implementng security or kernel mode for
the ARM platform.
o ARM/C5471 (arch/arm/src/c5471/)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
......
arch/arm/include/kinetis/irq.h
+ 248
− 15
View file @ bf0d9cd2
......@@ -58,24 +58,257 @@
/* Processor Exceptions (vectors 0-15) */
#define KINETIS_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define KINETIS_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define KINETIS_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define KINETIS_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define KINETIS_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define KINETIS_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define KINETIS_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define KINETIS_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define KINETIS_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define KINETIS_IRQ_SYSTICK (15) /* Vector 15: System tick */
#define KINETIS_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define KINETIS_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define KINETIS_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define KINETIS_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define KINETIS_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define KINETIS_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define KINETIS_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define KINETIS_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define KINETIS_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define KINETIS_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16) */
#warning "Missing logic"
#define NR_IRQS (16)
/* K40 Family ***********************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale document
* K40P144M100SF2RM
*/
#if defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) \
defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) \
defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */
# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */
# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */
# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */
# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */
# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */
# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */
# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */
# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */
# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */
# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */
# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */
# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */
# define KINETIS_IRQ_MCM (33) /* Vector 33: MCM Normal interrupt */
# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */
# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */
# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Ccntroller low-voltage
* detect, low-voltage warning */
# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */
# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */
/* Vector 39: Reserved */
# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */
# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */
# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */
# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */
# define KINETIS_IRQ_SPI2 (44) /* Vector 44: SPI2 all sources */
# define KINETIS_IRQ_CAN0MB (45) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */
# define KINETIS_IRQ_CAN0BO (46) /* Vector 46: CAN0 Bus Off */
# define KINETIS_IRQ_CAN0ERR (47) /* Vector 47: CAN0 Error */
# define KINETIS_IRQ_CAN0TW (48) /* Vector 48: CAN0 Transmit Warning */
# define KINETIS_IRQ_CAN0RW (49) /* Vector 49: CAN0 Receive Warning */
# define KINETIS_IRQ_CAN0WU (50) /* Vector 50: CAN0 Wake UP */
/* Vectors 51-52: Reserved */
# define KINETIS_IRQ_CAN1MB (53) /* Vector 53: CAN1 OR'ed Message buffer (0-15) */
# define KINETIS_IRQ_CAN1BO (54) /* Vector 54: CAN1 Bus Off */
# define KINETIS_IRQ_CAN1ERR (55) /* Vector 55: CAN1 Error */
# define KINETIS_IRQ_CAN1TW (56) /* Vector 56: CAN1 Transmit Warning */
# define KINETIS_IRQ_CAN1RW (57) /* Vector 57: CAN1 Receive Warning */
# define KINETIS_IRQ_CAN1WU (58) /* Vector 58: CAN1 Wake UP */
/* Vectors 59-60: Reserved */
# define KINETIS_IRQ_UART0S (61) /* Vector 61: UART0 status */
# define KINETIS_IRQ_UART0E (62) /* Vector 62: UART0 error */
# define KINETIS_IRQ_UART1S (63) /* Vector 63: UART1 status */
# define KINETIS_IRQ_UART1E (64) /* Vector 64: UART1 error */
# define KINETIS_IRQ_UART2S (65) /* Vector 65: UART2 status */
# define KINETIS_IRQ_UART2E (66) /* Vector 66: UART2 error */
# define KINETIS_IRQ_UART3S (67) /* Vector 67: UART3 status */
# define KINETIS_IRQ_UART3E (68) /* Vector 68: UART3 error */
# define KINETIS_IRQ_UART4S (69) /* Vector 69: UART4 status */
# define KINETIS_IRQ_UART4E (70) /* Vector 70: UART4 error */
# define KINETIS_IRQ_UART5S (71) /* Vector 71: UART5 status */
# define KINETIS_IRQ_UART5E (72) /* Vector 72: UART5 error */
# define KINETIS_IRQ_ADC0 (73) /* Vector 73: ADC0 */
# define KINETIS_IRQ_ADC1 (74) /* Vector 74: ADC1 */
# define KINETIS_IRQ_CMP0 (75) /* Vector 75: CMP0 */
# define KINETIS_IRQ_CMP1 (76) /* Vector 76: CMP1 */
# define KINETIS_IRQ_CMP2 (77) /* Vector 77: CMP2 */
# define KINETIS_IRQ_FTM0 (78) /* Vector 78: FTM0 all sources */
# define KINETIS_IRQ_FTM1 (79) /* Vector 79: FTM1 all sources */
# define KINETIS_IRQ_FTM2 (80) /* Vector 80: FTM2 all sources */
# define KINETIS_IRQ_CMT (81) /* Vector 81: CMT */
# define KINETIS_IRQ_RTC (82) /* Vector 82: RTC alarm interrupt */
/* Vector 83: Reserved */
# define KINETIS_IRQ_PITCH0 (84) /* Vector 84: PIT channel 0 */
# define KINETIS_IRQ_PITCH1 (85) /* Vector 85: PIT channel 1 */
# define KINETIS_IRQ_PITCH2 (86) /* Vector 86: PIT channel 2 */
# define KINETIS_IRQ_PITCH3 (87) /* Vector 87: PIT channel 3 */
# define KINETIS_IRQ_PDC (88) /* Vector 88: PDB */
# define KINETIS_IRQ_USBOTG (89) /* Vector 88: USB OTG */
# define KINETIS_IRQ_USBCD (90) /* Vector 90: USB charger detect */
/* Vectors 91-94: Reserved */
# define KINETIS_IRQ_I2S0 (95) /* Vector 95: I2S0 */
# define KINETIS_IRQ_SDHC (96) /* Vector 96: SDHC */
# define KINETIS_IRQ_DAC0 (97) /* Vector 97: DAC0 */
# define KINETIS_IRQ_DAC1 (98) /* Vector 98: DAC1 */
# define KINETIS_IRQ_TSI (99) /* Vector 97: TSI all sources */
# define KINETIS_IRQ_MCG (100) /* Vector 100: MCG */
# define KINETIS_IRQ_LPT (101) /* Vector 101: Low power timer */
# define KINETIS_IRQ_SLCD (102) /* Vector 102: Segment LCD all sources */
# define KINETIS_IRQ_PORTA (103) /* Vector 103: Pin detect port A */
# define KINETIS_IRQ_PORTB (104) /* Vector 104: Pin detect port B */
# define KINETIS_IRQ_PORTC (105) /* Vector 105: Pin detect port C */
# define KINETIS_IRQ_PORTD (106) /* Vector 106: Pin detect port D */
# define KINETIS_IRQ_PORTD (107) /* Vector 107: Pin detect port E */
/* Vectors 108-109: Reserved */
# define KINETIS_IRQ_SWI (110) /* Vector 110: Software interrupt */
/* Note that the total number of IRQ numbers supported is equal to the number of
* valid interrupt vectors. This is wasteful in that certain tables are sized by
* this value. There are only 94 valid interrupts so, potentially the numver of
* IRQs to could be reduced to 94. However, equating IRQ numbers with vector numbers
* also simplifies operations on NVIC registers and (at least in my state of mind
* now) seems to justify the waste.
*/
# define NR_IRQS (111) /* 111 vectors, 94 interrupts, 111 IRQ numbers */
/* K60 Family ***********************************************************************
*
* The memory map for the following parts is defined in Freescale document
* K60P144M100SF2RM
*/
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) \
defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) \
defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */
# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */
# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */
# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */
# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */
# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */
# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */
# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */
# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */
# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */
# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */
# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */
# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */
# define KINETIS_IRQ_MCM (33) /* Vector 33: MCM Normal interrupt */
# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */
# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */
# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Ccntroller low-voltage
* detect, low-voltage warning */
# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */
# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */
# define KINETIS_IRQ_RNGB (39) /* Vector 39: Random number generator */
# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */
# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */
# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */
# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */
# define KINETIS_IRQ_SPI2 (44) /* Vector 44: SPI2 all sources */
# define KINETIS_IRQ_CAN0MB (45) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */
# define KINETIS_IRQ_CAN0BO (46) /* Vector 46: CAN0 Bus Off */
# define KINETIS_IRQ_CAN0ERR (47) /* Vector 47: CAN0 Error */
# define KINETIS_IRQ_CAN0TW (48) /* Vector 48: CAN0 Transmit Warning */
# define KINETIS_IRQ_CAN0RW (49) /* Vector 49: CAN0 Receive Warning */
# define KINETIS_IRQ_CAN0WU (50) /* Vector 50: CAN0 Wake UP */
/* Vectors 51-52: Reserved */
# define KINETIS_IRQ_CAN1MB (53) /* Vector 53: CAN1 OR'ed Message buffer (0-15) */
# define KINETIS_IRQ_CAN1BO (54) /* Vector 54: CAN1 Bus Off */
# define KINETIS_IRQ_CAN1ERR (55) /* Vector 55: CAN1 Error */
# define KINETIS_IRQ_CAN1TW (56) /* Vector 56: CAN1 Transmit Warning */
# define KINETIS_IRQ_CAN1RW (57) /* Vector 57: CAN1 Receive Warning */
# define KINETIS_IRQ_CAN1WU (58) /* Vector 58: CAN1 Wake UP */
/* Vectors 59-60: Reserved */
# define KINETIS_IRQ_UART0S (61) /* Vector 61: UART0 status */
# define KINETIS_IRQ_UART0E (62) /* Vector 62: UART0 error */
# define KINETIS_IRQ_UART1S (63) /* Vector 63: UART1 status */
# define KINETIS_IRQ_UART1E (64) /* Vector 64: UART1 error */
# define KINETIS_IRQ_UART2S (65) /* Vector 65: UART2 status */
# define KINETIS_IRQ_UART2E (66) /* Vector 66: UART2 error */
# define KINETIS_IRQ_UART3S (67) /* Vector 67: UART3 status */
# define KINETIS_IRQ_UART3E (68) /* Vector 68: UART3 error */
# define KINETIS_IRQ_UART4S (69) /* Vector 69: UART4 status */
# define KINETIS_IRQ_UART4E (70) /* Vector 70: UART4 error */
# define KINETIS_IRQ_UART5S (71) /* Vector 71: UART5 status */
# define KINETIS_IRQ_UART5E (72) /* Vector 72: UART5 error */
# define KINETIS_IRQ_ADC0 (73) /* Vector 73: ADC0 */
# define KINETIS_IRQ_ADC1 (74) /* Vector 74: ADC1 */
# define KINETIS_IRQ_CMP0 (75) /* Vector 75: CMP0 */
# define KINETIS_IRQ_CMP1 (76) /* Vector 76: CMP1 */
# define KINETIS_IRQ_CMP2 (77) /* Vector 77: CMP2 */
# define KINETIS_IRQ_FTM0 (78) /* Vector 78: FTM0 all sources */
# define KINETIS_IRQ_FTM1 (79) /* Vector 79: FTM1 all sources */
# define KINETIS_IRQ_FTM2 (80) /* Vector 80: FTM2 all sources */
# define KINETIS_IRQ_CMT (81) /* Vector 81: CMT */
# define KINETIS_IRQ_RTC (82) /* Vector 82: RTC alarm interrupt */
/* Vector 83: Reserved */
# define KINETIS_IRQ_PITCH0 (84) /* Vector 84: PIT channel 0 */
# define KINETIS_IRQ_PITCH1 (85) /* Vector 85: PIT channel 1 */
# define KINETIS_IRQ_PITCH2 (86) /* Vector 86: PIT channel 2 */
# define KINETIS_IRQ_PITCH3 (87) /* Vector 87: PIT channel 3 */
# define KINETIS_IRQ_PDC (88) /* Vector 88: PDB */
# define KINETIS_IRQ_USBOTG (89) /* Vector 88: USB OTG */
# define KINETIS_IRQ_USBCD (90) /* Vector 90: USB charger detect */
# define KINETIS_IRQ_EMACTMR (91) /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */
# define KINETIS_IRQ_EMACTX (92) /* Vector 92: Ethernet MAC transmit interrupt */
# define KINETIS_IRQ_EMACRX (93) /* Vector 93: Ethernet MAC receive interrupt */
# define KINETIS_IRQ_EMACMISC (95) /* Vector 95: Ethernet MAC error and misc interrupt */
# define KINETIS_IRQ_I2S0 (95) /* Vector 95: I2S0 */
# define KINETIS_IRQ_SDHC (96) /* Vector 96: SDHC */
# define KINETIS_IRQ_DAC0 (97) /* Vector 97: DAC0 */
# define KINETIS_IRQ_DAC1 (98) /* Vector 98: DAC1 */
# define KINETIS_IRQ_TSI (99) /* Vector 97: TSI all sources */
# define KINETIS_IRQ_MCG (100) /* Vector 100: MCG */
# define KINETIS_IRQ_LPT (101) /* Vector 101: Low power timer */
/* Vector 102: Reserved */
# define KINETIS_IRQ_PORTA (103) /* Vector 103: Pin detect port A */
# define KINETIS_IRQ_PORTB (104) /* Vector 104: Pin detect port B */
# define KINETIS_IRQ_PORTC (105) /* Vector 105: Pin detect port C */
# define KINETIS_IRQ_PORTD (106) /* Vector 106: Pin detect port D */
# define KINETIS_IRQ_PORTD (107) /* Vector 107: Pin detect port E */
/* Vectors 108-119: Reserved */
/* Note that the total number of IRQ numbers supported is equal to the number of
* valid interrupt vectors. This is wasteful in that certain tables are sized by
* this value. There are only 94 valid interrupts so, potentially the numver of
* IRQs to could be reduced to 94. However, equating IRQ numbers with vector numbers
* also simplifies operations on NVIC registers and (at least in my state of mind
* now) seems to justify the waste.
*/
# define NR_IRQS (108)
# define NR_IRQS (111) /* 120 vectors, 97 interrupts, 108 IRQ numbers */
#else
/* The interrupt vectors for other parts are defined in other documents and may or
* may not be the same as above (the family members are all very similar) This
* error just means that you have to look at the document and determine for yourself
* if the memory map is the same.
*/
# error "No IRQ numbers for this Kinetis part"
#endif
/************************************************************************************
* Public Types
......
arch/arm/src/kinetis/chip.h
+ 3
− 3
View file @ bf0d9cd2
......@@ -828,12 +828,12 @@
#include "kinetis_memorymap.h"
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
/* Each priority field holds a priority value, 0-15. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
* bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
......
include/assert.h
+ 2
− 2
View file @ bf0d9cd2
/****************************************************************************
* include/assert.h
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
......@@ -50,9 +50,9 @@
/* Macro Name: ASSERT, ASSERTCODE, et al. */
#undef ASSERT
#undef ASSERTFILE
#undef ASSERTCODE
#undef DEBUGASSERT
#undef PANIC
#ifdef CONFIG_HAVE_FILENAME
......
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