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Commit fa253fbf authored by patacongo's avatar patacongo
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More PIC32 header files 

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3590 42af7a65-404d-4744-a932-0658087f49c3
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arch/mips/src/pic32mx/chip.h
+ 17
− 0
View file @ fa253fbf
......@@ -63,6 +63,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -86,6 +87,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -109,6 +111,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -132,6 +135,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -155,6 +159,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -178,6 +183,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -201,6 +207,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -224,6 +231,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -247,6 +255,7 @@
# define CHIP_VREG
# define CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -270,6 +279,7 @@
# define CHIP_VREG
# define CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -293,6 +303,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 1
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -316,6 +327,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 1
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -339,6 +351,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 1
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -362,6 +375,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 1
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -385,6 +399,7 @@
# define CHIP_VREG
# undef CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -408,6 +423,7 @@
# define CHIP_VREG
# define CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......@@ -431,6 +447,7 @@
# define CHIP_VREG
# define CHIP_TRACE
# define CHIP_NEUARTS 2
# define CHIP_UARTFIFOD 4
# define CHIP_NSPI 2
# define CHIP_NI2C 2
# define CHIP_NADC10 16
......
arch/mips/src/pic32mx/pic32mx-ioport.h 0 → 100755
+ 295
− 0
View file @ fa253fbf
This diff is collapsed.
arch/mips/src/pic32mx/pic32mx-memorymap.h
+ 18
− 18
View file @ fa253fbf
......@@ -176,24 +176,24 @@
/* Port Register Base Addresses */
#define PIC32MX_PORTA 0
#define PIC32MX_PORTB 1
#define PIC32MX_PORTC 2
#define PIC32MX_PORTD 3
#define PIC32MX_PORTE 4
#define PIC32MX_PORTF 5
#define PIC32MX_PORTG 6
#define PIC32MX_PORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x20*(n))
#define PIC32MX_PORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000)
#define PIC32MX_PORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040)
#define PIC32MX_PORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080)
#define PIC32MX_PORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0)
#define PIC32MX_PORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100)
#define PIC32MX_PORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140)
#define PIC32MX_PORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180)
#define PIC32MX_CNCON_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0)
#define PIC32MX_IOPORTA 0
#define PIC32MX_IOPORTB 1
#define PIC32MX_IOPORTC 2
#define PIC32MX_IOPORTD 3
#define PIC32MX_IOPORTE 4
#define PIC32MX_IOPORTF 5
#define PIC32MX_IOPORTG 6
#define PIC32MX_IOPORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x40*(n))
#define PIC32MX_IOPORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000)
#define PIC32MX_IOPORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040)
#define PIC32MX_IOPORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080)
#define PIC32MX_IOPORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0)
#define PIC32MX_IOPORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100)
#define PIC32MX_IOPORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140)
#define PIC32MX_IOPORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180)
#define PIC32MX_IOPORTCN_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0)
/****************************************************************************
* Public Types
......
arch/mips/src/pic32mx/pic32mx-uart.h 0 → 100755
+ 200
− 0
View file @ fa253fbf
/************************************************************************************
* arch/mips/src/pic32mx/pic32mx-uart.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_UART_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_UART_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "pic32mx-memorymap.h"
/************************************************************************************
* Pre-Processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define PIC32MX_UART_MODE_OFFSET 0x0000 /* UARTx mode register */
#define PIC32MX_UART_MODECLR_OFFSET 0x0004 /* UARTx mode clear register */
#define PIC32MX_UART_MODESET_OFFSET 0x0008 /* UARTx mode set register */
#define PIC32MX_UART_MODEINV_OFFSET 0x000c /* UARTx mode invert register */
#define PIC32MX_UART_STA_OFFSET 0x0010 /* UARTx status and control register */
#define PIC32MX_UART_STACLR_OFFSET 0x0014 /* UARTx status and control clear register */
#define PIC32MX_UART_STASET_OFFSET 0x0018 /* UARTx status and control set register */
#define PIC32MX_UART_STAINV_OFFSET 0x001c /* UARTx status and control invert register */
#define PIC32MX_UART_TXREG_OFFSET 0x0020 /* UARTx transmit register */
#define PIC32MX_UART_RXREG_OFFSET 0x0030 /* UARTx receive register */
#define PIC32MX_UART_BRG_OFFSET 0x0040 /* UARTx baud rate register */
#define PIC32MX_UART_BRGCLR_OFFSET 0x0044 /* UARTx baud rate clear register */
#define PIC32MX_UART_BRGSET_OFFSET 0x0048 /* UARTx baud rate set register */
#define PIC32MX_UART_BRGINV_OFFSET 0x004c /* UARTx baud rate invert register */
/* Register Addresses ****************************************************************/
#define PIC32MX_UART1_MODE (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODE_OFFSET)
#define PIC32MX_UART1_MODECLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODECLR_OFFSET)
#define PIC32MX_UART1_MODESET (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODESET_OFFSET)
#define PIC32MX_UART1_MODEINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODEINV_OFFSET)
#define PIC32MX_UART1_STA (PIC32MX_UART1_K1BASE+PIC32MX_UART_STA_OFFSET)
#define PIC32MX_UART1_STACLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_STACLR_OFFSET)
#define PIC32MX_UART1_STASET (PIC32MX_UART1_K1BASE+PIC32MX_UART_STASET_OFFSET)
#define PIC32MX_UART1_STAINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_STAINV_OFFSET)
#define PIC32MX_UART1_TXREG (PIC32MX_UART1_K1BASE+PIC32MX_UART_TXREG_OFFSET)
#define PIC32MX_UART1_RXREG (PIC32MX_UART1_K1BASE+PIC32MX_UART_RXREG_OFFSET)
#define PIC32MX_UART1_BRG (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRG_OFFSET)
#define PIC32MX_UART1_BRGCLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGCLR_OFFSET)
#define PIC32MX_UART1_BRGSET (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGSET_OFFSET)
#define PIC32MX_UART1_BRGINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGINV_OFFSET)
#define PIC32MX_UART2_MODE (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODE_OFFSET)
#define PIC32MX_UART2_MODECLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODECLR_OFFSET)
#define PIC32MX_UART2_MODESET (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODESET_OFFSET)
#define PIC32MX_UART2_MODEINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODEINV_OFFSET)
#define PIC32MX_UART2_STA (PIC32MX_UART2_K1BASE+PIC32MX_UART_STA_OFFSET)
#define PIC32MX_UART2_STACLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_STACLR_OFFSET)
#define PIC32MX_UART2_STASET (PIC32MX_UART2_K1BASE+PIC32MX_UART_STASET_OFFSET)
#define PIC32MX_UART2_STAINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_STAINV_OFFSET)
#define PIC32MX_UART2_TXREG (PIC32MX_UART2_K1BASE+PIC32MX_UART_TXREG_OFFSET)
#define PIC32MX_UART2_RXREG (PIC32MX_UART2_K1BASE+PIC32MX_UART_RXREG_OFFSET)
#define PIC32MX_UART2_BRG (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRG_OFFSET)
#define PIC32MX_UART2_BRGCLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGCLR_OFFSET)
#define PIC32MX_UART2_BRGSET (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGSET_OFFSET)
#define PIC32MX_UART2_BRGINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGINV_OFFSET)
/* Register Bit-Field Definitions ****************************************************/
/* UARTx mode register */
#define UART_MODE_STSEL (1 << 0) /* Bit 0: Stop selection 1=2 stop bits */
#define UART_MODE_PDSEL_SHIFT (1) /* Bits: 1-2: Parity and data selection */
#define UART_MODE_PDSEL_MASK (3 << UART_MODE_PDSEL_SHIFT)
# define UART_MODE_PDSEL_8NONE (0 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, no parity */
# define UART_MODE_PDSEL_8EVEN (1 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, even parity */
# define UART_MODE_PDSEL_8ODD (2 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, odd parity */
# define UART_MODE_PDSEL_9NONE (3 << UART_MODE_PDSEL_SHIFT) /* 9-bit data, no parity */
#define UART_MODE_BRGH (1 << 3) /* Bit 3: High baud rate enable */
#define UART_MODE_RXINV (1 << 4) /* Bit 4: Receive polarity inversion */
#define UART_MODE_ABAUD (1 << 5) /* Bit 5: Auto-baud enable */
#define UART_MODE_LPBACK (1 << 6) /* Bit 6: UARTx loopback mode select */
#define UART_MODE_WAKE (1 << 7) /* Bit 7: Enable wake-up on start bit detect during sleep mode */
#define UART_MODE_UEN_SHIFT (8) /* Bits: 8-9: UARTx enable */
#define UART_MODE_UEN_MASK (3 << UART_MODE_UEN_SHIFT)
# define UART_MODE_UEN_PORT (0 << UART_MODE_UEN_SHIFT) /* UxCTS+UxRTS/UxBCLK=PORTx register */
# define UART_MODE_UEN_ENR_CPORT (1 << UART_MODE_UEN_SHIFT) /* UxRTS=enabled; UxCTS=ORTx register */
# define UART_MODE_UEN_ENCR (2 << UART_MODE_UEN_SHIFT) /* UxCTS+UxRTS=enabled */
# define UART_MODE_UEN_CPORT (3 << UART_MODE_UEN_SHIFT) /* UxCTS=PORTx register */
#define UART_MODE_RTSMD (1 << 11) /* Bit 11: Mode selection for ~UxRTS pin */
#define UART_MODE_IREN (1 << 12) /* Bit 12: IrDA encoder and decoder enable */
#define UART_MODE_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
#define UART_MODE_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
#define UART_MODE_ON (1 << 15) /* Bit 15: UARTx enable */
/* UARTx status and control register */
#define UART_STA_URXDA (1 << 0) /* Bit 0: Receive buffer data available */
#define UART_STA_OERR (1 << 1) /* Bit 1: Receive buffer overrun error status */
#define UART_STA_FERR (1 << 2) /* Bit 2: Framing error status */
#define UART_STA_PERR (1 << 3) /* Bit 3: Parity error status */
#define UART_STA_RIDLE (1 << 4) /* Bit 4: Receiver idle */
#define UART_STA_ADDEN (1 << 5) /* Bit 5: Address character detect */
#define UART_STA_URXISEL_SHIFT (6) /* Bits: 6-7: Receive interrupt mode selection */
#define UART_STA_URXISEL_MASK (3 << UART_STA_URXISEL_SHIFT)
#if CHIP_UARTFIFOD == 4
# define UART_STA_URXISEL_RECVD (0 << UART_STA_URXISEL_SHIFT) /* Character received */
# define UART_STA_URXISEL_RXB3 (2 << UART_STA_URXISEL_SHIFT) /* RX buffer 3/4 */
# define UART_STA_URXISEL_RXBF (3 << UART_STA_URXISEL_SHIFT) /* RX buffer full */
#elif CHIP_UARTFIFOD == 8
# define UART_STA_URXISEL_RECVD (0 << UART_STA_URXISEL_SHIFT) /* Character received */
# define UART_STA_URXISEL_RXB4 (1 << UART_STA_URXISEL_SHIFT) /* RX buffer 1/2 */
# define UART_STA_URXISEL_RXB6 (2 << UART_STA_URXISEL_SHIFT) /* RX buffer 3/4 */
#endif
#define UART_STA_TRMT (1 << 8) /* Bit 8: Transmit shift register is empty */
#define UART_STA_UTXBF (1 << 9) /* Bit 9: Transmit buffer full status */
#define UART_STA_UTXEN (1 << 10) /* Bit 10: Transmit enable */
#define UART_STA_UTXBRK (1 << 11) /* Bit 11: Transmit break */
#define UART_STA_URXEN (1 << 12) /* Bit 12: Receiver enable */
#define UART_STA_UTXINV (1 << 13) /* Bit 13: Transmit polarity inversion */
#define UART_STA_UTXISEL_SHIFT (14) /* Bits: 14-15: TX interrupt mode selection bi */
#define UART_STA_UTXISEL_MASK (3 << UART_STA_UTXISEL_SHIFT)
# define UART_STA_UTXISEL_TXBNF (0 << UART_STA_UTXISEL_SHIFT) /* TX buffer not full */
# define UART_STA_UTXISEL_DRAINED (1 << UART_STA_UTXISEL_SHIFT) /* All characters sent */
# define UART_STA_UTXISEL_TXBE (2 << UART_STA_UTXISEL_SHIFT) /* TX buffer empty */
#define UART_STA_ADDR_SHIFT (16) /* Bits:16-23: Automatic address mask */
#define UART_STA_ADDR_MASK (0xff << UART_STA_ADDR_SHIFT)
#define UART_STA_ADM_EN (1 << 24) /* Bit 14: Automatic address detect mode enable */
/* UARTx transmit register */
#define UART_TXREG_MASK 0x1ff
/* UARTx receive register */
#define UART_RXREG_MASK 0x1ff
/* UARTx baud rate register */
#define UART_BRG_MASK 0xffff
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_UART_H */
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