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f4grx
NuttX RTOS
Commits
fc2deb11
Commit
fc2deb11
authored
7 years ago
by
Juha Niskanen
Committed by
Gregory Nutt
7 years ago
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STM32L4 serial: Allow configuring Rx DMA buffer size
parent
249ab6eb
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arch/arm/src/stm32l4/Kconfig
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12 additions, 0 deletions
arch/arm/src/stm32l4/Kconfig
arch/arm/src/stm32l4/stm32l4_serial.c
+10
-1
10 additions, 1 deletion
arch/arm/src/stm32l4/stm32l4_serial.c
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22 additions
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1 deletion
arch/arm/src/stm32l4/Kconfig
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fc2deb11
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@@ -3414,6 +3414,18 @@ config UART5_RXDMA
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config STM32L4_SERIAL_RXDMA_BUFFER_SIZE
int "Rx DMA buffer size"
default 32
depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA
---help---
The DMA buffer size when using RX DMA to emulate a FIFO.
When streaming data, the generic serial layer will be called
every time the FIFO receives half this number of bytes.
Value given here will be rounded up to next multiple of 32 bytes.
config SERIAL_DISABLE_REORDERING
bool "Disable reordering of ttySx devices."
depends on STM32L4_USART1 || STM32L4_USART2 || STM32L4_USART3 || STM32L4_UART4 || STM32L4_UART5
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arch/arm/src/stm32l4/stm32l4_serial.c
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fc2deb11
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@@ -133,9 +133,18 @@
*
* When streaming data, the generic serial layer will be called
* every time the FIFO receives half this number of bytes.
*
* If there ever is a STM32L4 with D-cache, the buffer size
* should be an even multiple of ARMV7M_DCACHE_LINESIZE, so that it
* can be individually invalidated.
*/
# define RXDMA_BUFFER_SIZE 32
# if !defined(CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE) || \
CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE == 0
# define RXDMA_BUFFER_SIZE 32
# else
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31)
# endif
/* DMA priority */
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