- Jul 23, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
SAMA5D3/4: All configurations. I suspect a MMC/SD multi-block DMA transfer issue. So for name, this feature is disabled in all configurations
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Gregory Nutt authored
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Gregory Nutt authored
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- Jul 22, 2014
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Gregory Nutt authored
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Gregory Nutt authored
Rename pcm_decode.h to pcm.h since it will hold more than just decoding definitions. Fix some porting errors like idbg should auddbg, etc. Add wav file header and a few low-level wav utilities.
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Gregory Nutt authored
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Gregory Nutt authored
Add new framework for the PCM decoder. It is now a 'front end' for lower-level drivers like the WM8904 that performs the PCM decoding from end
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
STM32 OTGFS device: Various changes to try to reduce that amount of time in interrupts handles and with interrupts disbled. Needs verification on other platforms. From Petteri Aimonen
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
Make sure that all sim configurations have CONFIG_SIM_M32 undefined. That is probably the wrong default setting, but we need to be consistent above all
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Gregory Nutt authored
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Gregory Nutt authored
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- Jul 21, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
SAMA5 HSMCI: Correct multi-block DMA setup; Fixes related to DMA timeout. Still problems with HSMCI DMA via XDMAC
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Gregory Nutt authored
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Gregory Nutt authored
SAMA4D5 HSMCI: Set burst size to 1, sample DMA registers on timeout, and don't return from transfer until BOTH the HSMCI transfer and DMA complete
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Gregory Nutt authored
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- Jul 20, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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- Jul 19, 2014
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Gregory Nutt authored
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Gregory Nutt authored
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Gregory Nutt authored
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