SAM3/4 and SAMV7 UART:  The IMR register is read-only.  This means that sam_restoreints() does not actually re-enable UART interrupts.

A side-effect of changing serial settings via TERMIOS (such as tcsetattr) is that serial interrupts were being left disabled.  This is not a problem if the serial configuration is changed when there are no open references to the serial device.  In that case, serial interrupts are disabled and will not be enabled enabled until the serial device is first opened.  But it is fatal if the serial device is already opened and if there is a task waiting to receive data.  In that case, the side-effect of disabling interrupts is fatal:  That task is then left hanging with interrupts disabled.

Implements CONFIG_TIME_EXTENDED as we discussed relative to providing the last 3 members of the tm struct and support for filling them in and even using the wday in the STM32 RTC. From David Sidrane.

Add conditional logic so that people who use F1 don't have to be bother with meaningless RTC MAGIC settings

SAMV7:  Apparently the data sheet is wrong, SDRAM clocking must be enabled at the PMC or the SDRAM does not work!  The data sheet says that there is no clock control for SDRAMC

More renaming: up_lcdinitialize->board_lcd_initialize, up_lcdgetdev->board_lcd_getdev, up_lcduninitialize->board_lcd_uninitialize

SAMV7: Add SMC register definition header file; SAMV71-Xult: Add an LCD driver.  The initial commit is simply the SAVM4E-EK ILI9375 driver will bogus name changes to ILI9488.

rch_tcinitialize() and arch_tcunitinitialize() renamed to board_tsc_setup() and board_tsc_teardown().  These are not long called directly by applications but only indirectly throught the crappy boardctl() OS interface.

SAMV71-XULT: Add option to support connection of the maXTouch Xplained Pro on the 50-pin LCD connector

The STM32F4Discovery board doesn't come with a Low speed external oscillator so the default LSE source for the RTC doesn't work.

In stm32_rtcc.c the up_rtcinitialize() logic doesn't work with the LSI. The check on RTC_MAGIC on the BK0R register lead to rtc_setup() call that rightfully enables the lsi clock; but the next times, when the rtc is already setup, the rtc_resume() call does NOT start the lsi clock!

The right place to put LSE/LSI initialisation is inside stm32_stdclockconfig() in stm32fxxxxx_rcc.c.  Doing this I checked the possible uses of the LSI and the LSE sources: the LSI can be used for RTC and/or the IWDG, while the LSE only for the RTC (and to output the MCO1 pin)..

This change is not verifed for any other platforms.

From Leo Aloe3132

SAMV7 Ethernet:  I- and D-Cache are now enabled in the netnsh/ configuration.  D-Cache is enabled in write-though mode.  This mode is necessary because the DMA descriptors are each 8-bytes in size but the D-Cache cache line is 32-bits in size. So it is impossible make coherency for every 8-byte DMA descriptor without write-through.