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main.out:     file format elf32-littlearm


Disassembly of section .text:

08008000 <SystemInit>:
  *         SystemFrequency variable.
  * @param  None
  * @retval None
  */
void SystemInit(void)
{
 8008000:	b580      	push	{r7, lr}
 8008002:	af00      	add	r7, sp, #0
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
  #endif
  /* Reset the RCC clock configuration to the default reset state ------------*/
  /* Set HSION bit */
  RCC->CR |= (uint32_t)0x00000001;
 8008004:	4a13      	ldr	r2, [pc, #76]	(8008054 <SystemInit+0x54>)
 8008006:	4b13      	ldr	r3, [pc, #76]	(8008054 <SystemInit+0x54>)
 8008008:	681b      	ldr	r3, [r3, #0]
 800800a:	f043 0301 	orr.w	r3, r3, #1	; 0x1
 800800e:	6013      	str	r3, [r2, #0]

  /* Reset CFGR register */
  RCC->CFGR = 0x00000000;
 8008010:	4a10      	ldr	r2, [pc, #64]	(8008054 <SystemInit+0x54>)
 8008012:	f04f 0300 	mov.w	r3, #0	; 0x0
 8008016:	6093      	str	r3, [r2, #8]

  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= (uint32_t)0xFEF6FFFF;
 8008018:	4a0e      	ldr	r2, [pc, #56]	(8008054 <SystemInit+0x54>)
 800801a:	4b0e      	ldr	r3, [pc, #56]	(8008054 <SystemInit+0x54>)
 800801c:	681b      	ldr	r3, [r3, #0]
 800801e:	f023 7384 	bic.w	r3, r3, #17301504	; 0x1080000
 8008022:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8008026:	6013      	str	r3, [r2, #0]

  /* Reset PLLCFGR register */
  RCC->PLLCFGR = 0x24003010;
 8008028:	4a0a      	ldr	r2, [pc, #40]	(8008054 <SystemInit+0x54>)
 800802a:	4b0b      	ldr	r3, [pc, #44]	(8008058 <SystemInit+0x58>)
 800802c:	6053      	str	r3, [r2, #4]

  /* Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFF;
 800802e:	4a09      	ldr	r2, [pc, #36]	(8008054 <SystemInit+0x54>)
 8008030:	4b08      	ldr	r3, [pc, #32]	(8008054 <SystemInit+0x54>)
 8008032:	681b      	ldr	r3, [r3, #0]
 8008034:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8008038:	6013      	str	r3, [r2, #0]

  /* Disable all interrupts */
  RCC->CIR = 0x00000000;
 800803a:	4a06      	ldr	r2, [pc, #24]	(8008054 <SystemInit+0x54>)
 800803c:	f04f 0300 	mov.w	r3, #0	; 0x0
 8008040:	60d3      	str	r3, [r2, #12]
  SystemInit_ExtMemCtl(); 
#endif /* DATA_IN_ExtSRAM */
         
  /* Configure the System clock source, PLL Multiplier and Divider factors, 
     AHB/APBx prescalers and Flash settings ----------------------------------*/
  SetSysClock();
 8008042:	f000 f89b 	bl	800817c <SetSysClock>

  /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 8008046:	4a05      	ldr	r2, [pc, #20]	(800805c <SystemInit+0x5c>)
 8008048:	f04f 6300 	mov.w	r3, #134217728	; 0x8000000
 800804c:	6093      	str	r3, [r2, #8]
#endif
}
 800804e:	46bd      	mov	sp, r7
 8008050:	bd80      	pop	{r7, pc}
 8008052:	46c0      	nop			(mov r8, r8)
 8008054:	40023800 	.word	0x40023800
 8008058:	24003010 	.word	0x24003010
 800805c:	e000ed00 	.word	0xe000ed00

08008060 <SystemCoreClockUpdate>:
  *     
  * @param  None
  * @retval None
  */
void SystemCoreClockUpdate(void)
{
 8008060:	b480      	push	{r7}
 8008062:	b089      	sub	sp, #36
 8008064:	af00      	add	r7, sp, #0
  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
 8008066:	f04f 0300 	mov.w	r3, #0	; 0x0
 800806a:	60fb      	str	r3, [r7, #12]
 800806c:	f04f 0300 	mov.w	r3, #0	; 0x0
 8008070:	613b      	str	r3, [r7, #16]
 8008072:	f04f 0302 	mov.w	r3, #2	; 0x2
 8008076:	617b      	str	r3, [r7, #20]
 8008078:	f04f 0300 	mov.w	r3, #0	; 0x0
 800807c:	61bb      	str	r3, [r7, #24]
 800807e:	f04f 0302 	mov.w	r3, #2	; 0x2
 8008082:	61fb      	str	r3, [r7, #28]
  
  /* Get SYSCLK source -------------------------------------------------------*/
  tmp = RCC->CFGR & RCC_CFGR_SWS;
 8008084:	4b38      	ldr	r3, [pc, #224]	(8008168 <SystemCoreClockUpdate+0x108>)
 8008086:	689b      	ldr	r3, [r3, #8]
 8008088:	f003 030c 	and.w	r3, r3, #12	; 0xc
 800808c:	60fb      	str	r3, [r7, #12]

  switch (tmp)
 800808e:	68fb      	ldr	r3, [r7, #12]
 8008090:	607b      	str	r3, [r7, #4]
 8008092:	687b      	ldr	r3, [r7, #4]
 8008094:	2b04      	cmp	r3, #4
 8008096:	d009      	beq.n	80080ac <SystemCoreClockUpdate+0x4c>
 8008098:	687b      	ldr	r3, [r7, #4]
 800809a:	2b08      	cmp	r3, #8
 800809c:	d00a      	beq.n	80080b4 <SystemCoreClockUpdate+0x54>
 800809e:	687b      	ldr	r3, [r7, #4]
 80080a0:	2b00      	cmp	r3, #0
 80080a2:	d147      	bne.n	8008134 <SystemCoreClockUpdate+0xd4>
  {
    case 0x00:  /* HSI used as system clock source */
      SystemCoreClock = HSI_VALUE;
 80080a4:	4a31      	ldr	r2, [pc, #196]	(800816c <SystemCoreClockUpdate+0x10c>)
 80080a6:	4b32      	ldr	r3, [pc, #200]	(8008170 <SystemCoreClockUpdate+0x110>)
 80080a8:	6013      	str	r3, [r2, #0]
 80080aa:	e046      	b.n	800813a <SystemCoreClockUpdate+0xda>
      break;
    case 0x04:  /* HSE used as system clock source */
      SystemCoreClock = HSE_VALUE;
 80080ac:	4a2f      	ldr	r2, [pc, #188]	(800816c <SystemCoreClockUpdate+0x10c>)
 80080ae:	4b31      	ldr	r3, [pc, #196]	(8008174 <SystemCoreClockUpdate+0x114>)
 80080b0:	6013      	str	r3, [r2, #0]
 80080b2:	e042      	b.n	800813a <SystemCoreClockUpdate+0xda>
    case 0x08:  /* PLL used as system clock source */

      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
         SYSCLK = PLL_VCO / PLL_P
         */    
      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 80080b4:	4b2c      	ldr	r3, [pc, #176]	(8008168 <SystemCoreClockUpdate+0x108>)
 80080b6:	685b      	ldr	r3, [r3, #4]
 80080b8:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 80080bc:	ea4f 5393 	mov.w	r3, r3, lsr #22
 80080c0:	61bb      	str	r3, [r7, #24]
      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 80080c2:	4b29      	ldr	r3, [pc, #164]	(8008168 <SystemCoreClockUpdate+0x108>)
 80080c4:	685b      	ldr	r3, [r3, #4]
 80080c6:	f003 033f 	and.w	r3, r3, #63	; 0x3f
 80080ca:	61fb      	str	r3, [r7, #28]
      
      if (pllsource != 0)
 80080cc:	69bb      	ldr	r3, [r7, #24]
 80080ce:	2b00      	cmp	r3, #0
 80080d0:	d00f      	beq.n	80080f2 <SystemCoreClockUpdate+0x92>
      {
        /* HSE used as PLL clock source */
        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 80080d2:	4a28      	ldr	r2, [pc, #160]	(8008174 <SystemCoreClockUpdate+0x114>)
 80080d4:	69fb      	ldr	r3, [r7, #28]
 80080d6:	fbb2 f1f3 	udiv	r1, r2, r3
 80080da:	4b23      	ldr	r3, [pc, #140]	(8008168 <SystemCoreClockUpdate+0x108>)
 80080dc:	685a      	ldr	r2, [r3, #4]
 80080de:	f647 73c0 	movw	r3, #32704	; 0x7fc0
 80080e2:	ea02 0303 	and.w	r3, r2, r3
 80080e6:	ea4f 1393 	mov.w	r3, r3, lsr #6
 80080ea:	fb03 f301 	mul.w	r3, r3, r1
 80080ee:	613b      	str	r3, [r7, #16]
 80080f0:	e00e      	b.n	8008110 <SystemCoreClockUpdate+0xb0>
      }
      else
      {
        /* HSI used as PLL clock source */
        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
 80080f2:	4a1f      	ldr	r2, [pc, #124]	(8008170 <SystemCoreClockUpdate+0x110>)
 80080f4:	69fb      	ldr	r3, [r7, #28]
 80080f6:	fbb2 f1f3 	udiv	r1, r2, r3
 80080fa:	4b1b      	ldr	r3, [pc, #108]	(8008168 <SystemCoreClockUpdate+0x108>)
 80080fc:	685a      	ldr	r2, [r3, #4]
 80080fe:	f647 73c0 	movw	r3, #32704	; 0x7fc0
 8008102:	ea02 0303 	and.w	r3, r2, r3
 8008106:	ea4f 1393 	mov.w	r3, r3, lsr #6
 800810a:	fb03 f301 	mul.w	r3, r3, r1
 800810e:	613b      	str	r3, [r7, #16]
      }

      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
 8008110:	4b15      	ldr	r3, [pc, #84]	(8008168 <SystemCoreClockUpdate+0x108>)
 8008112:	685b      	ldr	r3, [r3, #4]
 8008114:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
 8008118:	ea4f 4313 	mov.w	r3, r3, lsr #16
 800811c:	f103 0301 	add.w	r3, r3, #1	; 0x1
 8008120:	ea4f 0343 	mov.w	r3, r3, lsl #1
 8008124:	617b      	str	r3, [r7, #20]
      SystemCoreClock = pllvco/pllp;
 8008126:	693a      	ldr	r2, [r7, #16]
 8008128:	697b      	ldr	r3, [r7, #20]
 800812a:	fbb2 f2f3 	udiv	r2, r2, r3
 800812e:	4b0f      	ldr	r3, [pc, #60]	(800816c <SystemCoreClockUpdate+0x10c>)
 8008130:	601a      	str	r2, [r3, #0]
 8008132:	e002      	b.n	800813a <SystemCoreClockUpdate+0xda>
      break;
    default:
      SystemCoreClock = HSI_VALUE;
 8008134:	4a0d      	ldr	r2, [pc, #52]	(800816c <SystemCoreClockUpdate+0x10c>)
 8008136:	4b0e      	ldr	r3, [pc, #56]	(8008170 <SystemCoreClockUpdate+0x110>)
 8008138:	6013      	str	r3, [r2, #0]
      break;
  }
  /* Compute HCLK frequency --------------------------------------------------*/
  /* Get HCLK prescaler */
  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 800813a:	4b0b      	ldr	r3, [pc, #44]	(8008168 <SystemCoreClockUpdate+0x108>)
 800813c:	689b      	ldr	r3, [r3, #8]
 800813e:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 8008142:	ea4f 1213 	mov.w	r2, r3, lsr #4
 8008146:	4b0c      	ldr	r3, [pc, #48]	(8008178 <SystemCoreClockUpdate+0x118>)
 8008148:	5c9b      	ldrb	r3, [r3, r2]
 800814a:	b2db      	uxtb	r3, r3
 800814c:	60fb      	str	r3, [r7, #12]
  /* HCLK frequency */
  SystemCoreClock >>= tmp;
 800814e:	4b07      	ldr	r3, [pc, #28]	(800816c <SystemCoreClockUpdate+0x10c>)
 8008150:	681a      	ldr	r2, [r3, #0]
 8008152:	68fb      	ldr	r3, [r7, #12]
 8008154:	fa22 f203 	lsr.w	r2, r2, r3
 8008158:	4b04      	ldr	r3, [pc, #16]	(800816c <SystemCoreClockUpdate+0x10c>)
 800815a:	601a      	str	r2, [r3, #0]
}
 800815c:	f107 0724 	add.w	r7, r7, #36	; 0x24
 8008160:	46bd      	mov	sp, r7
 8008162:	bc80      	pop	{r7}
 8008164:	4770      	bx	lr
 8008166:	46c0      	nop			(mov r8, r8)
 8008168:	40023800 	.word	0x40023800
 800816c:	20000000 	.word	0x20000000
 8008170:	00f42400 	.word	0x00f42400
 8008174:	007a1200 	.word	0x007a1200
 8008178:	20000004 	.word	0x20000004

0800817c <SetSysClock>:
  *         is reset to the default reset state (done in SystemInit() function).   
  * @param  None
  * @retval None
  */
static void SetSysClock(void)
{
 800817c:	b480      	push	{r7}
 800817e:	b083      	sub	sp, #12
 8008180:	af00      	add	r7, sp, #0
/******************************************************************************/
/*            PLL (clocked by HSE) used as System clock source                */
/******************************************************************************/
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 8008182:	f04f 0300 	mov.w	r3, #0	; 0x0
 8008186:	607b      	str	r3, [r7, #4]
 8008188:	f04f 0300 	mov.w	r3, #0	; 0x0
 800818c:	603b      	str	r3, [r7, #0]
  
  /* Enable HSE */
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 800818e:	4a36      	ldr	r2, [pc, #216]	(8008268 <SetSysClock+0xec>)
 8008190:	4b35      	ldr	r3, [pc, #212]	(8008268 <SetSysClock+0xec>)
 8008192:	681b      	ldr	r3, [r3, #0]
 8008194:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8008198:	6013      	str	r3, [r2, #0]
 
  /* Wait till HSE is ready and if Time out is reached exit */
  do
  {
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
 800819a:	4b33      	ldr	r3, [pc, #204]	(8008268 <SetSysClock+0xec>)
 800819c:	681b      	ldr	r3, [r3, #0]
 800819e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80081a2:	603b      	str	r3, [r7, #0]
    StartUpCounter++;
 80081a4:	687b      	ldr	r3, [r7, #4]
 80081a6:	f103 0301 	add.w	r3, r3, #1	; 0x1
 80081aa:	607b      	str	r3, [r7, #4]
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 80081ac:	683b      	ldr	r3, [r7, #0]
 80081ae:	2b00      	cmp	r3, #0
 80081b0:	d103      	bne.n	80081ba <SetSysClock+0x3e>
 80081b2:	687b      	ldr	r3, [r7, #4]
 80081b4:	f5b3 4fa0 	cmp.w	r3, #20480	; 0x5000
 80081b8:	d1ef      	bne.n	800819a <SetSysClock+0x1e>

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 80081ba:	4b2b      	ldr	r3, [pc, #172]	(8008268 <SetSysClock+0xec>)
 80081bc:	681b      	ldr	r3, [r3, #0]
 80081be:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80081c2:	2b00      	cmp	r3, #0
 80081c4:	d003      	beq.n	80081ce <SetSysClock+0x52>
  {
    HSEStatus = (uint32_t)0x01;
 80081c6:	f04f 0301 	mov.w	r3, #1	; 0x1
 80081ca:	603b      	str	r3, [r7, #0]
 80081cc:	e002      	b.n	80081d4 <SetSysClock+0x58>
  }
  else
  {
    HSEStatus = (uint32_t)0x00;
 80081ce:	f04f 0300 	mov.w	r3, #0	; 0x0
 80081d2:	603b      	str	r3, [r7, #0]
  }

  if (HSEStatus == (uint32_t)0x01)
 80081d4:	683b      	ldr	r3, [r7, #0]
 80081d6:	2b01      	cmp	r3, #1
 80081d8:	d140      	bne.n	800825c <SetSysClock+0xe0>
  {
    /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
 80081da:	4a23      	ldr	r2, [pc, #140]	(8008268 <SetSysClock+0xec>)
 80081dc:	4b22      	ldr	r3, [pc, #136]	(8008268 <SetSysClock+0xec>)
 80081de:	6c1b      	ldr	r3, [r3, #64]
 80081e0:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 80081e4:	6413      	str	r3, [r2, #64]
    PWR->CR |= PWR_CR_VOS;
 80081e6:	4a21      	ldr	r2, [pc, #132]	(800826c <SetSysClock+0xf0>)
 80081e8:	4b20      	ldr	r3, [pc, #128]	(800826c <SetSysClock+0xf0>)
 80081ea:	681b      	ldr	r3, [r3, #0]
 80081ec:	f443 4340 	orr.w	r3, r3, #49152	; 0xc000
 80081f0:	6013      	str	r3, [r2, #0]

    /* HCLK = SYSCLK / 1*/
    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
 80081f2:	4a1d      	ldr	r2, [pc, #116]	(8008268 <SetSysClock+0xec>)
 80081f4:	4b1c      	ldr	r3, [pc, #112]	(8008268 <SetSysClock+0xec>)
 80081f6:	689b      	ldr	r3, [r3, #8]
 80081f8:	6093      	str	r3, [r2, #8]
      
    /* PCLK2 = HCLK / 2*/
    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
 80081fa:	4a1b      	ldr	r2, [pc, #108]	(8008268 <SetSysClock+0xec>)
 80081fc:	4b1a      	ldr	r3, [pc, #104]	(8008268 <SetSysClock+0xec>)
 80081fe:	689b      	ldr	r3, [r3, #8]
 8008200:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
 8008204:	6093      	str	r3, [r2, #8]
    
    /* PCLK1 = HCLK / 4*/
    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
 8008206:	4a18      	ldr	r2, [pc, #96]	(8008268 <SetSysClock+0xec>)
 8008208:	4b17      	ldr	r3, [pc, #92]	(8008268 <SetSysClock+0xec>)
 800820a:	689b      	ldr	r3, [r3, #8]
 800820c:	f443 53a0 	orr.w	r3, r3, #5120	; 0x1400
 8008210:	6093      	str	r3, [r2, #8]

    /* Configure the main PLL */
    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
 8008212:	4a15      	ldr	r2, [pc, #84]	(8008268 <SetSysClock+0xec>)
 8008214:	4b16      	ldr	r3, [pc, #88]	(8008270 <SetSysClock+0xf4>)
 8008216:	6053      	str	r3, [r2, #4]
                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);

    /* Enable the main PLL */
    RCC->CR |= RCC_CR_PLLON;
 8008218:	4a13      	ldr	r2, [pc, #76]	(8008268 <SetSysClock+0xec>)
 800821a:	4b13      	ldr	r3, [pc, #76]	(8008268 <SetSysClock+0xec>)
 800821c:	681b      	ldr	r3, [r3, #0]
 800821e:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
 8008222:	6013      	str	r3, [r2, #0]

    /* Wait till the main PLL is ready */
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
 8008224:	4b10      	ldr	r3, [pc, #64]	(8008268 <SetSysClock+0xec>)
 8008226:	681b      	ldr	r3, [r3, #0]
 8008228:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 800822c:	2b00      	cmp	r3, #0
 800822e:	d0f9      	beq.n	8008224 <SetSysClock+0xa8>
    {
    }
   
    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
    FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
 8008230:	4a10      	ldr	r2, [pc, #64]	(8008274 <SetSysClock+0xf8>)
 8008232:	f240 6305 	movw	r3, #1541	; 0x605
 8008236:	6013      	str	r3, [r2, #0]

    /* Select the main PLL as system clock source */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 8008238:	4a0b      	ldr	r2, [pc, #44]	(8008268 <SetSysClock+0xec>)
 800823a:	4b0b      	ldr	r3, [pc, #44]	(8008268 <SetSysClock+0xec>)
 800823c:	689b      	ldr	r3, [r3, #8]
 800823e:	f023 0303 	bic.w	r3, r3, #3	; 0x3
 8008242:	6093      	str	r3, [r2, #8]
    RCC->CFGR |= RCC_CFGR_SW_PLL;
 8008244:	4a08      	ldr	r2, [pc, #32]	(8008268 <SetSysClock+0xec>)
 8008246:	4b08      	ldr	r3, [pc, #32]	(8008268 <SetSysClock+0xec>)
 8008248:	689b      	ldr	r3, [r3, #8]
 800824a:	f043 0302 	orr.w	r3, r3, #2	; 0x2
 800824e:	6093      	str	r3, [r2, #8]

    /* Wait till the main PLL is used as system clock source */
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
 8008250:	4b05      	ldr	r3, [pc, #20]	(8008268 <SetSysClock+0xec>)
 8008252:	689b      	ldr	r3, [r3, #8]
 8008254:	f003 030c 	and.w	r3, r3, #12	; 0xc
 8008258:	2b08      	cmp	r3, #8
 800825a:	d1f9      	bne.n	8008250 <SetSysClock+0xd4>
  else
  { /* If HSE fails to start-up, the application will have wrong clock
         configuration. User can add here some code to deal with this error */
  }

}
 800825c:	f107 070c 	add.w	r7, r7, #12	; 0xc
 8008260:	46bd      	mov	sp, r7
 8008262:	bc80      	pop	{r7}
 8008264:	4770      	bx	lr
 8008266:	46c0      	nop			(mov r8, r8)
 8008268:	40023800 	.word	0x40023800
 800826c:	40007000 	.word	0x40007000
 8008270:	07405408 	.word	0x07405408
 8008274:	40023c00 	.word	0x40023c00

08008278 <NVIC_PriorityGroupConfig>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
  *         The pending IRQ priority will be managed only by the subpriority. 
  * @retval None
  */
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
 8008278:	b480      	push	{r7}
 800827a:	b083      	sub	sp, #12
 800827c:	af00      	add	r7, sp, #0
 800827e:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  //assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
  
  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
 8008280:	4a05      	ldr	r2, [pc, #20]	(8008298 <NVIC_PriorityGroupConfig+0x20>)
 8008282:	687b      	ldr	r3, [r7, #4]
 8008284:	f043 63be 	orr.w	r3, r3, #99614720	; 0x5f00000
 8008288:	f443 2320 	orr.w	r3, r3, #655360	; 0xa0000
 800828c:	60d3      	str	r3, [r2, #12]
}
 800828e:	f107 070c 	add.w	r7, r7, #12	; 0xc
 8008292:	46bd      	mov	sp, r7
 8008294:	bc80      	pop	{r7}
 8008296:	4770      	bx	lr
 8008298:	e000ed00 	.word	0xe000ed00

0800829c <NVIC_Init>:
  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
  *         the configuration information for the specified NVIC peripheral.
  * @retval None
  */
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
 800829c:	b480      	push	{r7}
 800829e:	b085      	sub	sp, #20
 80082a0:	af00      	add	r7, sp, #0
 80082a2:	6078      	str	r0, [r7, #4]
  uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
 80082a4:	f04f 0300 	mov.w	r3, #0	; 0x0
 80082a8:	737b      	strb	r3, [r7, #13]
 80082aa:	f04f 0300 	mov.w	r3, #0	; 0x0
 80082ae:	73bb      	strb	r3, [r7, #14]
 80082b0:	f04f 030f 	mov.w	r3, #15	; 0xf
 80082b4:	73fb      	strb	r3, [r7, #15]
  /* Check the parameters */
  //assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
  //assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
  //assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
    
  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
 80082b6:	687b      	ldr	r3, [r7, #4]
 80082b8:	78db      	ldrb	r3, [r3, #3]
 80082ba:	2b00      	cmp	r3, #0
 80082bc:	d03f      	beq.n	800833e <NVIC_Init+0xa2>
  {
    /* Compute the Corresponding IRQ Priority --------------------------------*/    
    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
 80082be:	4b2c      	ldr	r3, [pc, #176]	(8008370 <NVIC_Init+0xd4>)
 80082c0:	68db      	ldr	r3, [r3, #12]
 80082c2:	ea6f 0303 	mvn.w	r3, r3
 80082c6:	f403 63e0 	and.w	r3, r3, #1792	; 0x700
 80082ca:	ea4f 2313 	mov.w	r3, r3, lsr #8
 80082ce:	737b      	strb	r3, [r7, #13]
    tmppre = (0x4 - tmppriority);
 80082d0:	7b7b      	ldrb	r3, [r7, #13]
 80082d2:	f1c3 0304 	rsb	r3, r3, #4	; 0x4
 80082d6:	73bb      	strb	r3, [r7, #14]
    tmpsub = tmpsub >> tmppriority;
 80082d8:	7bfa      	ldrb	r2, [r7, #15]
 80082da:	7b7b      	ldrb	r3, [r7, #13]
 80082dc:	fa42 f303 	asr.w	r3, r2, r3
 80082e0:	73fb      	strb	r3, [r7, #15]

    tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
 80082e2:	687b      	ldr	r3, [r7, #4]
 80082e4:	785b      	ldrb	r3, [r3, #1]
 80082e6:	461a      	mov	r2, r3
 80082e8:	7bbb      	ldrb	r3, [r7, #14]
 80082ea:	fa02 f303 	lsl.w	r3, r2, r3
 80082ee:	737b      	strb	r3, [r7, #13]
    tmppriority |=  (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
 80082f0:	687b      	ldr	r3, [r7, #4]
 80082f2:	789a      	ldrb	r2, [r3, #2]
 80082f4:	7bfb      	ldrb	r3, [r7, #15]
 80082f6:	ea02 0303 	and.w	r3, r2, r3
 80082fa:	b2da      	uxtb	r2, r3
 80082fc:	7b7b      	ldrb	r3, [r7, #13]
 80082fe:	ea42 0303 	orr.w	r3, r2, r3
 8008302:	737b      	strb	r3, [r7, #13]
        
    tmppriority = tmppriority << 0x04;
 8008304:	7b7b      	ldrb	r3, [r7, #13]
 8008306:	ea4f 1303 	mov.w	r3, r3, lsl #4
 800830a:	737b      	strb	r3, [r7, #13]
        
    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
 800830c:	4a19      	ldr	r2, [pc, #100]	(8008374 <NVIC_Init+0xd8>)
 800830e:	687b      	ldr	r3, [r7, #4]
 8008310:	781b      	ldrb	r3, [r3, #0]
 8008312:	441a      	add	r2, r3
 8008314:	7b7b      	ldrb	r3, [r7, #13]
 8008316:	f882 3300 	strb.w	r3, [r2, #768]
    
    /* Enable the Selected IRQ Channels --------------------------------------*/
    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
 800831a:	4816      	ldr	r0, [pc, #88]	(8008374 <NVIC_Init+0xd8>)
 800831c:	687b      	ldr	r3, [r7, #4]
 800831e:	781b      	ldrb	r3, [r3, #0]
 8008320:	ea4f 1353 	mov.w	r3, r3, lsr #5
 8008324:	b2db      	uxtb	r3, r3
 8008326:	4619      	mov	r1, r3
 8008328:	687b      	ldr	r3, [r7, #4]
 800832a:	781b      	ldrb	r3, [r3, #0]
 800832c:	f003 021f 	and.w	r2, r3, #31	; 0x1f
 8008330:	f04f 0301 	mov.w	r3, #1	; 0x1
 8008334:	fa03 f302 	lsl.w	r3, r3, r2
 8008338:	f840 3021 	str.w	r3, [r0, r1, lsl #2]
 800833c:	e012      	b.n	8008364 <NVIC_Init+0xc8>
      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
  }
  else
  {
    /* Disable the Selected IRQ Channels -------------------------------------*/
    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
 800833e:	480d      	ldr	r0, [pc, #52]	(8008374 <NVIC_Init+0xd8>)
 8008340:	687b      	ldr	r3, [r7, #4]
 8008342:	781b      	ldrb	r3, [r3, #0]
 8008344:	ea4f 1353 	mov.w	r3, r3, lsr #5
 8008348:	b2db      	uxtb	r3, r3
 800834a:	4619      	mov	r1, r3
 800834c:	687b      	ldr	r3, [r7, #4]
 800834e:	781b      	ldrb	r3, [r3, #0]
 8008350:	f003 021f 	and.w	r2, r3, #31	; 0x1f
 8008354:	f04f 0301 	mov.w	r3, #1	; 0x1
 8008358:	fa03 f202 	lsl.w	r2, r3, r2
 800835c:	f101 0320 	add.w	r3, r1, #32	; 0x20
 8008360:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
  }
}
 8008364:	f107 0714 	add.w	r7, r7, #20	; 0x14
 8008368:	46bd      	mov	sp, r7
 800836a:	bc80      	pop	{r7}
 800836c:	4770      	bx	lr
 800836e:	46c0      	nop			(mov r8, r8)
 8008370:	e000ed00 	.word	0xe000ed00
 8008374:	e000e100 	.word	0xe000e100

08008378 <NVIC_SetVectorTable>:
  *     @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
  * @param  Offset: Vector Table base offset field. This value must be a multiple of 0x200.
  * @retval None
  */
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
{ 
 8008378:	b480      	push	{r7}
 800837a:	b083      	sub	sp, #12
 800837c:	af00      	add	r7, sp, #0
 800837e:	6078      	str	r0, [r7, #4]
 8008380:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  //assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
  //assert_param(IS_NVIC_OFFSET(Offset));  
   
  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
 8008382:	4907      	ldr	r1, [pc, #28]	(80083a0 <NVIC_SetVectorTable+0x28>)
 8008384:	683b      	ldr	r3, [r7, #0]
 8008386:	f023 4360 	bic.w	r3, r3, #3758096384	; 0xe0000000
 800838a:	f023 037f 	bic.w	r3, r3, #127	; 0x7f
 800838e:	687a      	ldr	r2, [r7, #4]
 8008390:	ea43 0302 	orr.w	r3, r3, r2
 8008394:	608b      	str	r3, [r1, #8]
}
 8008396:	f107 070c 	add.w	r7, r7, #12	; 0xc
 800839a:	46bd      	mov	sp, r7
 800839c:	bc80      	pop	{r7}
 800839e:	4770      	bx	lr
 80083a0:	e000ed00 	.word	0xe000ed00

080083a4 <NVIC_SystemLPConfig>:
  *     @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
{
 80083a4:	b480      	push	{r7}
 80083a6:	b083      	sub	sp, #12
 80083a8:	af00      	add	r7, sp, #0
 80083aa:	4603      	mov	r3, r0
 80083ac:	460a      	mov	r2, r1
 80083ae:	71fb      	strb	r3, [r7, #7]
 80083b0:	4613      	mov	r3, r2
 80083b2:	71bb      	strb	r3, [r7, #6]
  /* Check the parameters */
  //assert_param(IS_NVIC_LP(LowPowerMode));
  //assert_param(IS_FUNCTIONAL_STATE(NewState));  
  
  if (NewState != DISABLE)
 80083b4:	79bb      	ldrb	r3, [r7, #6]
 80083b6:	2b00      	cmp	r3, #0
 80083b8:	d007      	beq.n	80083ca <NVIC_SystemLPConfig+0x26>
  {
    SCB->SCR |= LowPowerMode;
 80083ba:	490b      	ldr	r1, [pc, #44]	(80083e8 <NVIC_SystemLPConfig+0x44>)
 80083bc:	4b0a      	ldr	r3, [pc, #40]	(80083e8 <NVIC_SystemLPConfig+0x44>)
 80083be:	691a      	ldr	r2, [r3, #16]
 80083c0:	79fb      	ldrb	r3, [r7, #7]
 80083c2:	ea42 0303 	orr.w	r3, r2, r3
 80083c6:	610b      	str	r3, [r1, #16]
 80083c8:	e008      	b.n	80083dc <NVIC_SystemLPConfig+0x38>
  }
  else
  {
    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
 80083ca:	4907      	ldr	r1, [pc, #28]	(80083e8 <NVIC_SystemLPConfig+0x44>)
 80083cc:	4b06      	ldr	r3, [pc, #24]	(80083e8 <NVIC_SystemLPConfig+0x44>)
 80083ce:	691a      	ldr	r2, [r3, #16]
 80083d0:	79fb      	ldrb	r3, [r7, #7]
 80083d2:	ea6f 0303 	mvn.w	r3, r3
 80083d6:	ea02 0303 	and.w	r3, r2, r3
 80083da:	610b      	str	r3, [r1, #16]
  }
}
 80083dc:	f107 070c 	add.w	r7, r7, #12	; 0xc
 80083e0:	46bd      	mov	sp, r7
 80083e2:	bc80      	pop	{r7}
 80083e4:	4770      	bx	lr
 80083e6:	46c0      	nop			(mov r8, r8)
 80083e8:	e000ed00 	.word	0xe000ed00

080083ec <SysTick_CLKSourceConfig>:
  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
  * @retval None
  */
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
{
 80083ec:	b480      	push	{r7}
 80083ee:	b083      	sub	sp, #12
 80083f0:	af00      	add	r7, sp, #0
 80083f2:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  //assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
 80083f4:	687b      	ldr	r3, [r7, #4]
 80083f6:	2b04      	cmp	r3, #4
 80083f8:	d106      	bne.n	8008408 <SysTick_CLKSourceConfig+0x1c>
  {
    SysTick->CTRL |= SysTick_CLKSource_HCLK;
 80083fa:	4a09      	ldr	r2, [pc, #36]	(8008420 <SysTick_CLKSourceConfig+0x34>)
 80083fc:	4b08      	ldr	r3, [pc, #32]	(8008420 <SysTick_CLKSourceConfig+0x34>)
 80083fe:	681b      	ldr	r3, [r3, #0]
 8008400:	f043 0304 	orr.w	r3, r3, #4	; 0x4
 8008404:	6013      	str	r3, [r2, #0]
 8008406:	e005      	b.n	8008414 <SysTick_CLKSourceConfig+0x28>
  }
  else
  {
    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
 8008408:	4a05      	ldr	r2, [pc, #20]	(8008420 <SysTick_CLKSourceConfig+0x34>)
 800840a:	4b05      	ldr	r3, [pc, #20]	(8008420 <SysTick_CLKSourceConfig+0x34>)
 800840c:	681b      	ldr	r3, [r3, #0]
 800840e:	f023 0304 	bic.w	r3, r3, #4	; 0x4
 8008412:	6013      	str	r3, [r2, #0]
  }
}
 8008414:	f107 070c 	add.w	r7, r7, #12	; 0xc
 8008418:	46bd      	mov	sp, r7
 800841a:	bc80      	pop	{r7}
 800841c:	4770      	bx	lr
 800841e:	46c0      	nop			(mov r8, r8)
 8008420:	e000e010 	.word	0xe000e010

08008424 <ADC_DeInit>:
  *         values.
  * @param  None
  * @retval None
  */
void ADC_DeInit(void)
{
 8008424:	b580      	push	{r7, lr}
 8008426:	af00      	add	r7, sp, #0
  /* Enable all ADCs reset state */
  RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);
 8008428:	f44f 7080 	mov.w	r0, #256	; 0x100
 800842c:	f04f 0101 	mov.w	r1, #1	; 0x1
 8008430:	f002 facc 	bl	800a9cc <RCC_APB2PeriphResetCmd>
  
  /* Release all ADCs from reset state */
  RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);
 8008434:	f44f 7080 	mov.w	r0, #256	; 0x100
 8008438:	f04f 0100 	mov.w	r1, #0	; 0x0
 800843c:	f002 fac6 	bl	800a9cc <RCC_APB2PeriphResetCmd>
}
 8008440:	46bd      	mov	sp, r7
 8008442:	bd80      	pop	{r7, pc}

08008444 <ADC_Init>:
  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
  *         the configuration information for the specified ADC peripheral.
  * @retval None
  */
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
{
 8008444:	b480      	push	{r7}
 8008446:	b085      	sub	sp, #20
 8008448:	af00      	add	r7, sp, #0
 800844a:	6078      	str	r0, [r7, #4]
 800844c:	6039      	str	r1, [r7, #0]
  uint32_t tmpreg1 = 0;
 800844e:	f04f 0300 	mov.w	r3, #0	; 0x0
 8008452:	60bb      	str	r3, [r7, #8]
  uint8_t tmpreg2 = 0;
 8008454:	f04f 0300 	mov.w	r3, #0	; 0x0
 8008458:	73fb      	strb	r3, [r7, #15]
  //assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); 
  //assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
  
  /*---------------------------- ADCx CR1 Configuration -----------------*/
  /* Get the ADCx CR1 value */
  tmpreg1 = ADCx->CR1;
 800845a:	687b      	ldr	r3, [r7, #4]
 800845c:	685b      	ldr	r3, [r3, #4]
 800845e:	60bb      	str	r3, [r7, #8]
  
  /* Clear RES and SCAN bits */
  tmpreg1 &= CR1_CLEAR_MASK;
 8008460:	68bb      	ldr	r3, [r7, #8]
 8008462:	f023 7340 	bic.w	r3, r3, #50331648	; 0x3000000
 8008466:	f423 7380 	bic.w	r3, r3, #256	; 0x100
 800846a:	60bb      	str	r3, [r7, #8]
  
  /* Configure ADCx: scan conversion mode and resolution */
  /* Set SCAN bit according to ADC_ScanConvMode value */
  /* Set RES bit according to ADC_Resolution value */ 
  tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
 800846c:	683b      	ldr	r3, [r7, #0]
 800846e:	791b      	ldrb	r3, [r3, #4]
 8008470:	ea4f 2203 	mov.w	r2, r3, lsl #8
 8008474:	683b      	ldr	r3, [r7, #0]
 8008476:	681b      	ldr	r3, [r3, #0]
 8008478:	ea42 0203 	orr.w	r2, r2, r3
 800847c:	68bb      	ldr	r3, [r7, #8]
 800847e:	ea43 0302 	orr.w	r3, r3, r2
 8008482:	60bb      	str	r3, [r7, #8]
                                   ADC_InitStruct->ADC_Resolution);
  /* Write to ADCx CR1 */
  ADCx->CR1 = tmpreg1;
 8008484:	687a      	ldr	r2, [r7, #4]
 8008486:	68bb      	ldr	r3, [r7, #8]
 8008488:	6053      	str	r3, [r2, #4]
  /*---------------------------- ADCx CR2 Configuration -----------------*/
  /* Get the ADCx CR2 value */
  tmpreg1 = ADCx->CR2;
 800848a:	687b      	ldr	r3, [r7, #4]
 800848c:	689b      	ldr	r3, [r3, #8]
 800848e:	60bb      	str	r3, [r7, #8]
  
  /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
  tmpreg1 &= CR2_CLEAR_MASK;
 8008490:	68ba      	ldr	r2, [r7, #8]
 8008492:	4b1d      	ldr	r3, [pc, #116]	(8008508 <ADC_Init+0xc4>)
 8008494:	ea02 0303 	and.w	r3, r2, r3
 8008498:	60bb      	str	r3, [r7, #8]
     continuous conversion mode */
  /* Set ALIGN bit according to ADC_DataAlign value */
  /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ 
  /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
  /* Set CONT bit according to ADC_ContinuousConvMode value */
  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
 800849a:	683b      	ldr	r3, [r7, #0]
 800849c:	691a      	ldr	r2, [r3, #16]
 800849e:	683b      	ldr	r3, [r7, #0]
 80084a0:	68db      	ldr	r3, [r3, #12]
 80084a2:	ea42 0203 	orr.w	r2, r2, r3
 80084a6:	683b      	ldr	r3, [r7, #0]
 80084a8:	689b      	ldr	r3, [r3, #8]
 80084aa:	ea42 0203 	orr.w	r2, r2, r3
 80084ae:	683b      	ldr	r3, [r7, #0]
 80084b0:	795b      	ldrb	r3, [r3, #5]
 80084b2:	ea4f 0343 	mov.w	r3, r3, lsl #1
 80084b6:	ea42 0203 	orr.w	r2, r2, r3
 80084ba:	68bb      	ldr	r3, [r7, #8]
 80084bc:	ea43 0302 	orr.w	r3, r3, r2
 80084c0:	60bb      	str	r3, [r7, #8]
                        ADC_InitStruct->ADC_ExternalTrigConv | 
                        ADC_InitStruct->ADC_ExternalTrigConvEdge | \
                        ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
                        
  /* Write to ADCx CR2 */
  ADCx->CR2 = tmpreg1;
 80084c2:	687a      	ldr	r2, [r7, #4]
 80084c4:	68bb      	ldr	r3, [r7, #8]
 80084c6:	6093      	str	r3, [r2, #8]
  /*---------------------------- ADCx SQR1 Configuration -----------------*/
  /* Get the ADCx SQR1 value */
  tmpreg1 = ADCx->SQR1;
 80084c8:	687b      	ldr	r3, [r7, #4]
 80084ca:	6adb      	ldr	r3, [r3, #44]
 80084cc:	60bb      	str	r3, [r7, #8]
  
  /* Clear L bits */
  tmpreg1 &= SQR1_L_RESET;
 80084ce:	68bb      	ldr	r3, [r7, #8]
 80084d0:	f423 0370 	bic.w	r3, r3, #15728640	; 0xf00000
 80084d4:	60bb      	str	r3, [r7, #8]
  
  /* Configure ADCx: regular channel sequence length */
  /* Set L bits according to ADC_NbrOfConversion value */
  tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
 80084d6:	683b      	ldr	r3, [r7, #0]
 80084d8:	7d1b      	ldrb	r3, [r3, #20]
 80084da:	f103 33ff 	add.w	r3, r3, #4294967295	; 0xffffffff
 80084de:	b2da      	uxtb	r2, r3
 80084e0:	7bfb      	ldrb	r3, [r7, #15]
 80084e2:	ea42 0303 	orr.w	r3, r2, r3
 80084e6:	73fb      	strb	r3, [r7, #15]
  tmpreg1 |= ((uint32_t)tmpreg2 << 20);
 80084e8:	7bfb      	ldrb	r3, [r7, #15]
 80084ea:	ea4f 5203 	mov.w	r2, r3, lsl #20
 80084ee:	68bb      	ldr	r3, [r7, #8]
 80084f0:	ea43 0302 	orr.w	r3, r3, r2
 80084f4:	60bb      	str	r3, [r7, #8]
  
  /* Write to ADCx SQR1 */
  ADCx->SQR1 = tmpreg1;
 80084f6:	687a      	ldr	r2, [r7, #4]
 80084f8:	68bb      	ldr	r3, [r7, #8]
 80084fa:	62d3      	str	r3, [r2, #44]
}
 80084fc:	f107 0714 	add.w	r7, r7, #20	; 0x14
 8008500:	46bd      	mov	sp, r7
 8008502:	bc80      	pop	{r7}
 8008504:	4770      	bx	lr
 8008506:	46c0      	nop			(mov r8, r8)
 8008508:	c0fff7fd 	.word	0xc0fff7fd

0800850c <ADC_StructInit>:
  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will 
  *         be initialized.
  * @retval None
  */
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
{
 800850c:	b480      	push	{r7}
 800850e:	b083      	sub	sp, #12
 8008510:	af00      	add	r7, sp, #0
 8008512:	6078      	str	r0, [r7, #4]
  /* Initialize the ADC_Mode member */
  ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
 8008514:	687a      	ldr	r2, [r7, #4]
 8008516:	f04f 0300 	mov.w	r3, #0	; 0x0
 800851a:	6013      	str	r3, [r2, #0]

  /* initialize the ADC_ScanConvMode member */
  ADC_InitStruct->ADC_ScanConvMode = DISABLE;
 800851c:	687a      	ldr	r2, [r7, #4]
 800851e:	f04f 0300 	mov.w	r3, #0	; 0x0
 8008522:	7113      	strb	r3, [r2, #4]

  /* Initialize the ADC_ContinuousConvMode member */
  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
 8008524:	687a      	ldr	r2, [r7, #4]
 8008526:	f04f 0300 	mov.w	r3, #0	; 0x0
 800852a:	7153      	strb	r3, [r2, #5]

  /* Initialize the ADC_ExternalTrigConvEdge member */
  ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
 800852c:	687a      	ldr	r2, [r7, #4]
 800852e:	f04f 0300 	mov.w	r3, #0	; 0x0
 8008532:	6093      	str	r3, [r2, #8]

  /* Initialize the ADC_ExternalTrigConv member */
  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
 8008534:	687a      	ldr	r2, [r7, #4]
 8008536:	f04f 0300 	mov.w	r3, #0	; 0x0
 800853a:	60d3      	str	r3, [r2, #12]

  /* Initialize the ADC_DataAlign member */
  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
 800853c:	687a      	ldr	r2, [r7, #4]
 800853e:	f04f 0300 	mov.w	r3, #0	; 0x0
 8008542:	6113      	str	r3, [r2, #16]

  /* Initialize the ADC_NbrOfConversion member */
  ADC_InitStruct->ADC_NbrOfConversion = 1;
 8008544:	687a      	ldr	r2, [r7, #4]
 8008546:	f04f 0301 	mov.w	r3, #1	; 0x1
 800854a:	7513      	strb	r3, [r2, #20]
}
 800854c:	f107 070c 	add.w	r7, r7, #12	; 0xc
 8008550:	46bd      	mov	sp, r7
 8008552:	bc80      	pop	{r7}
 8008554:	4770      	bx	lr
 8008556:	46c0      	nop			(mov r8, r8)

08008558 <ADC_CommonInit>:
  * @param  ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure 
  *         that contains the configuration information for  All ADCs peripherals.
  * @retval None
  */
void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
{
 8008558:	b480      	push	{r7}
 800855a:	b085      	sub	sp, #20
 800855c:	af00      	add	r7, sp, #0
 800855e:	6078      	str	r0, [r7, #4]
  uint32_t tmpreg1 = 0;
 8008560:	f04f 0300 	mov.w	r3, #0	; 0x0
 8008564:	60fb      	str	r3, [r7, #12]
  //assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
  //assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
  //assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
  /*---------------------------- ADC CCR Configuration -----------------*/
  /* Get the ADC CCR value */
  tmpreg1 = ADC->CCR;
 8008566:	4b11      	ldr	r3, [pc, #68]	(80085ac <ADC_CommonInit+0x54>)
 8008568:	685b      	ldr	r3, [r3, #4]
 800856a:	60fb      	str	r3, [r7, #12]
  
  /* Clear MULTI, DELAY, DMA and ADCPRE bits */
  tmpreg1 &= CR_CLEAR_MASK;
 800856c:	68fa      	ldr	r2, [r7, #12]
 800856e:	4b10      	ldr	r3, [pc, #64]	(80085b0 <ADC_CommonInit+0x58>)
 8008570:	ea02 0303 	and.w	r3, r2, r3
 8008574:	60fb      	str	r3, [r7, #12]
     and DMA access mode for multimode */
  /* Set MULTI bits according to ADC_Mode value */
  /* Set ADCPRE bits according to ADC_Prescaler value */
  /* Set DMA bits according to ADC_DMAAccessMode value */
  /* Set DELAY bits according to ADC_TwoSamplingDelay value */    
  tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | 
 8008576:	687b      	ldr	r3, [r7, #4]
 8008578:	681a      	ldr	r2, [r3, #0]
 800857a:	687b      	ldr	r3, [r7, #4]
 800857c:	685b      	ldr	r3, [r3, #4]
 800857e:	ea42 0203 	orr.w	r2, r2, r3
 8008582:	687b      	ldr	r3, [r7, #4]
 8008584:	689b      	ldr	r3, [r3, #8]
 8008586:	ea42 0203 	orr.w	r2, r2, r3
 800858a:	687b      	ldr	r3, [r7, #4]
 800858c:	68db      	ldr	r3, [r3, #12]
 800858e:	ea42 0203 	orr.w	r2, r2, r3
 8008592:	68fb      	ldr	r3, [r7, #12]
 8008594:	ea43 0302 	orr.w	r3, r3, r2
 8008598:	60fb      	str	r3, [r7, #12]
                        ADC_CommonInitStruct->ADC_Prescaler | 
                        ADC_CommonInitStruct->ADC_DMAAccessMode | 
                        ADC_CommonInitStruct->ADC_TwoSamplingDelay);
                        
  /* Write to ADC CCR */
  ADC->CCR = tmpreg1;
 800859a:	4a04      	ldr	r2, [pc, #16]	(80085ac <ADC_CommonInit+0x54>)
 800859c:	68fb      	ldr	r3, [r7, #12]
 800859e:	6053      	str	r3, [r2, #4]
}
 80085a0:	f107 0714 	add.w	r7, r7, #20	; 0x14
 80085a4:	46bd      	mov	sp, r7
 80085a6:	bc80      	pop	{r7}
 80085a8:	4770      	bx	lr
 80085aa:	46c0      	nop			(mov r8, r8)
 80085ac:	40012300 	.word	0x40012300
 80085b0:	fffc30e0 	.word	0xfffc30e0

080085b4 <ADC_CommonStructInit>:
  * @param  ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
  *         which will be initialized.
  * @retval None
  */
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
{
 80085b4:	b480      	push	{r7}
 80085b6:	b083      	sub	sp, #12
 80085b8:	af00      	add	r7, sp, #0
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