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800900a: 6153 str r3, [r2, #20]
/* Reset interrupt pending bits for the selected stream */
if (DMAy_Streamx == DMA1_Stream0)
800900c: 687a ldr r2, [r7, #4]
800900e: 4b46 ldr r3, [pc, #280] (8009128 <DMA_DeInit+0x160>)
8009010: 429a cmp r2, r3
8009012: d104 bne.n 800901e <DMA_DeInit+0x56>
{
/* Reset interrupt pending bits for DMA1 Stream0 */
DMA1->LIFCR = DMA_Stream0_IT_MASK;
8009014: 4a45 ldr r2, [pc, #276] (800912c <DMA_DeInit+0x164>)
8009016: f04f 033d mov.w r3, #61 ; 0x3d
800901a: 6093 str r3, [r2, #8]
800901c: e07f b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA1_Stream1)
800901e: 687a ldr r2, [r7, #4]
8009020: 4b43 ldr r3, [pc, #268] (8009130 <DMA_DeInit+0x168>)
8009022: 429a cmp r2, r3
8009024: d104 bne.n 8009030 <DMA_DeInit+0x68>
{
/* Reset interrupt pending bits for DMA1 Stream1 */
DMA1->LIFCR = DMA_Stream1_IT_MASK;
8009026: 4a41 ldr r2, [pc, #260] (800912c <DMA_DeInit+0x164>)
8009028: f44f 6374 mov.w r3, #3904 ; 0xf40
800902c: 6093 str r3, [r2, #8]
800902e: e076 b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA1_Stream2)
8009030: 687a ldr r2, [r7, #4]
8009032: 4b40 ldr r3, [pc, #256] (8009134 <DMA_DeInit+0x16c>)
8009034: 429a cmp r2, r3
8009036: d104 bne.n 8009042 <DMA_DeInit+0x7a>
{
/* Reset interrupt pending bits for DMA1 Stream2 */
DMA1->LIFCR = DMA_Stream2_IT_MASK;
8009038: 4a3c ldr r2, [pc, #240] (800912c <DMA_DeInit+0x164>)
800903a: f44f 1374 mov.w r3, #3997696 ; 0x3d0000
800903e: 6093 str r3, [r2, #8]
8009040: e06d b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA1_Stream3)
8009042: 687a ldr r2, [r7, #4]
8009044: 4b3c ldr r3, [pc, #240] (8009138 <DMA_DeInit+0x170>)
8009046: 429a cmp r2, r3
8009048: d104 bne.n 8009054 <DMA_DeInit+0x8c>
{
/* Reset interrupt pending bits for DMA1 Stream3 */
DMA1->LIFCR = DMA_Stream3_IT_MASK;
800904a: 4a38 ldr r2, [pc, #224] (800912c <DMA_DeInit+0x164>)
800904c: f04f 6374 mov.w r3, #255852544 ; 0xf400000
8009050: 6093 str r3, [r2, #8]
8009052: e064 b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA1_Stream4)
8009054: 687a ldr r2, [r7, #4]
8009056: 4b39 ldr r3, [pc, #228] (800913c <DMA_DeInit+0x174>)
8009058: 429a cmp r2, r3
800905a: d103 bne.n 8009064 <DMA_DeInit+0x9c>
{
/* Reset interrupt pending bits for DMA1 Stream4 */
DMA1->HIFCR = DMA_Stream4_IT_MASK;
800905c: 4a33 ldr r2, [pc, #204] (800912c <DMA_DeInit+0x164>)
800905e: 4b38 ldr r3, [pc, #224] (8009140 <DMA_DeInit+0x178>)
8009060: 60d3 str r3, [r2, #12]
8009062: e05c b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA1_Stream5)
8009064: 687a ldr r2, [r7, #4]
8009066: 4b37 ldr r3, [pc, #220] (8009144 <DMA_DeInit+0x17c>)
8009068: 429a cmp r2, r3
800906a: d103 bne.n 8009074 <DMA_DeInit+0xac>
{
/* Reset interrupt pending bits for DMA1 Stream5 */
DMA1->HIFCR = DMA_Stream5_IT_MASK;
800906c: 4a2f ldr r2, [pc, #188] (800912c <DMA_DeInit+0x164>)
800906e: 4b36 ldr r3, [pc, #216] (8009148 <DMA_DeInit+0x180>)
8009070: 60d3 str r3, [r2, #12]
8009072: e054 b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA1_Stream6)
8009074: 687a ldr r2, [r7, #4]
8009076: 4b35 ldr r3, [pc, #212] (800914c <DMA_DeInit+0x184>)
8009078: 429a cmp r2, r3
800907a: d103 bne.n 8009084 <DMA_DeInit+0xbc>
{
/* Reset interrupt pending bits for DMA1 Stream6 */
DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
800907c: 4a2b ldr r2, [pc, #172] (800912c <DMA_DeInit+0x164>)
800907e: 4b34 ldr r3, [pc, #208] (8009150 <DMA_DeInit+0x188>)
8009080: 60d3 str r3, [r2, #12]
8009082: e04c b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA1_Stream7)
8009084: 687a ldr r2, [r7, #4]
8009086: 4b33 ldr r3, [pc, #204] (8009154 <DMA_DeInit+0x18c>)
8009088: 429a cmp r2, r3
800908a: d104 bne.n 8009096 <DMA_DeInit+0xce>
{
/* Reset interrupt pending bits for DMA1 Stream7 */
DMA1->HIFCR = DMA_Stream7_IT_MASK;
800908c: 4a27 ldr r2, [pc, #156] (800912c <DMA_DeInit+0x164>)
800908e: f04f 533d mov.w r3, #792723456 ; 0x2f400000
8009092: 60d3 str r3, [r2, #12]
8009094: e043 b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA2_Stream0)
8009096: 687a ldr r2, [r7, #4]
8009098: 4b2f ldr r3, [pc, #188] (8009158 <DMA_DeInit+0x190>)
800909a: 429a cmp r2, r3
800909c: d104 bne.n 80090a8 <DMA_DeInit+0xe0>
{
/* Reset interrupt pending bits for DMA2 Stream0 */
DMA2->LIFCR = DMA_Stream0_IT_MASK;
800909e: 4a2f ldr r2, [pc, #188] (800915c <DMA_DeInit+0x194>)
80090a0: f04f 033d mov.w r3, #61 ; 0x3d
80090a4: 6093 str r3, [r2, #8]
80090a6: e03a b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA2_Stream1)
80090a8: 687a ldr r2, [r7, #4]
80090aa: 4b2d ldr r3, [pc, #180] (8009160 <DMA_DeInit+0x198>)
80090ac: 429a cmp r2, r3
80090ae: d104 bne.n 80090ba <DMA_DeInit+0xf2>
{
/* Reset interrupt pending bits for DMA2 Stream1 */
DMA2->LIFCR = DMA_Stream1_IT_MASK;
80090b0: 4a2a ldr r2, [pc, #168] (800915c <DMA_DeInit+0x194>)
80090b2: f44f 6374 mov.w r3, #3904 ; 0xf40
80090b6: 6093 str r3, [r2, #8]
80090b8: e031 b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA2_Stream2)
80090ba: 687a ldr r2, [r7, #4]
80090bc: 4b29 ldr r3, [pc, #164] (8009164 <DMA_DeInit+0x19c>)
80090be: 429a cmp r2, r3
80090c0: d104 bne.n 80090cc <DMA_DeInit+0x104>
{
/* Reset interrupt pending bits for DMA2 Stream2 */
DMA2->LIFCR = DMA_Stream2_IT_MASK;
80090c2: 4a26 ldr r2, [pc, #152] (800915c <DMA_DeInit+0x194>)
80090c4: f44f 1374 mov.w r3, #3997696 ; 0x3d0000
80090c8: 6093 str r3, [r2, #8]
80090ca: e028 b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA2_Stream3)
80090cc: 687a ldr r2, [r7, #4]
80090ce: 4b26 ldr r3, [pc, #152] (8009168 <DMA_DeInit+0x1a0>)
80090d0: 429a cmp r2, r3
80090d2: d104 bne.n 80090de <DMA_DeInit+0x116>
{
/* Reset interrupt pending bits for DMA2 Stream3 */
DMA2->LIFCR = DMA_Stream3_IT_MASK;
80090d4: 4a21 ldr r2, [pc, #132] (800915c <DMA_DeInit+0x194>)
80090d6: f04f 6374 mov.w r3, #255852544 ; 0xf400000
80090da: 6093 str r3, [r2, #8]
80090dc: e01f b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA2_Stream4)
80090de: 687a ldr r2, [r7, #4]
80090e0: 4b22 ldr r3, [pc, #136] (800916c <DMA_DeInit+0x1a4>)
80090e2: 429a cmp r2, r3
80090e4: d103 bne.n 80090ee <DMA_DeInit+0x126>
{
/* Reset interrupt pending bits for DMA2 Stream4 */
DMA2->HIFCR = DMA_Stream4_IT_MASK;
80090e6: 4a1d ldr r2, [pc, #116] (800915c <DMA_DeInit+0x194>)
80090e8: 4b15 ldr r3, [pc, #84] (8009140 <DMA_DeInit+0x178>)
80090ea: 60d3 str r3, [r2, #12]
80090ec: e017 b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA2_Stream5)
80090ee: 687a ldr r2, [r7, #4]
80090f0: 4b1f ldr r3, [pc, #124] (8009170 <DMA_DeInit+0x1a8>)
80090f2: 429a cmp r2, r3
80090f4: d103 bne.n 80090fe <DMA_DeInit+0x136>
{
/* Reset interrupt pending bits for DMA2 Stream5 */
DMA2->HIFCR = DMA_Stream5_IT_MASK;
80090f6: 4a19 ldr r2, [pc, #100] (800915c <DMA_DeInit+0x194>)
80090f8: 4b13 ldr r3, [pc, #76] (8009148 <DMA_DeInit+0x180>)
80090fa: 60d3 str r3, [r2, #12]
80090fc: e00f b.n 800911e <DMA_DeInit+0x156>
}
else if (DMAy_Streamx == DMA2_Stream6)
80090fe: 687a ldr r2, [r7, #4]
8009100: 4b1c ldr r3, [pc, #112] (8009174 <DMA_DeInit+0x1ac>)
8009102: 429a cmp r2, r3
8009104: d103 bne.n 800910e <DMA_DeInit+0x146>
{
/* Reset interrupt pending bits for DMA2 Stream6 */
DMA2->HIFCR = DMA_Stream6_IT_MASK;
8009106: 4a15 ldr r2, [pc, #84] (800915c <DMA_DeInit+0x194>)
8009108: 4b11 ldr r3, [pc, #68] (8009150 <DMA_DeInit+0x188>)
800910a: 60d3 str r3, [r2, #12]
800910c: e007 b.n 800911e <DMA_DeInit+0x156>
}
else
{
if (DMAy_Streamx == DMA2_Stream7)
800910e: 687a ldr r2, [r7, #4]
8009110: 4b19 ldr r3, [pc, #100] (8009178 <DMA_DeInit+0x1b0>)
8009112: 429a cmp r2, r3
8009114: d103 bne.n 800911e <DMA_DeInit+0x156>
{
/* Reset interrupt pending bits for DMA2 Stream7 */
DMA2->HIFCR = DMA_Stream7_IT_MASK;
8009116: 4a11 ldr r2, [pc, #68] (800915c <DMA_DeInit+0x194>)
8009118: f04f 533d mov.w r3, #792723456 ; 0x2f400000
800911c: 60d3 str r3, [r2, #12]
}
}
}
800911e: f107 070c add.w r7, r7, #12 ; 0xc
8009122: 46bd mov sp, r7
8009124: bc80 pop {r7}
8009126: 4770 bx lr
8009128: 40026010 .word 0x40026010
800912c: 40026000 .word 0x40026000
8009130: 40026028 .word 0x40026028
8009134: 40026040 .word 0x40026040
8009138: 40026058 .word 0x40026058
800913c: 40026070 .word 0x40026070
8009140: 2000003d .word 0x2000003d
8009144: 40026088 .word 0x40026088
8009148: 20000f40 .word 0x20000f40
800914c: 400260a0 .word 0x400260a0
8009150: 203d0000 .word 0x203d0000
8009154: 400260b8 .word 0x400260b8
8009158: 40026410 .word 0x40026410
800915c: 40026400 .word 0x40026400
8009160: 40026428 .word 0x40026428
8009164: 40026440 .word 0x40026440
8009168: 40026458 .word 0x40026458
800916c: 40026470 .word 0x40026470
8009170: 40026488 .word 0x40026488
8009174: 400264a0 .word 0x400264a0
8009178: 400264b8 .word 0x400264b8
0800917c <DMA_Init>:
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval None
*/
void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct)
{
800917c: b480 push {r7}
800917e: b085 sub sp, #20
8009180: af00 add r7, sp, #0
8009182: 6078 str r0, [r7, #4]
8009184: 6039 str r1, [r7, #0]
uint32_t tmpreg = 0;
8009186: f04f 0300 mov.w r3, #0 ; 0x0
800918a: 60fb str r3, [r7, #12]
//assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst));
//assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst));
/*------------------------- DMAy Streamx CR Configuration ------------------*/
/* Get the DMAy_Streamx CR value */
tmpreg = DMAy_Streamx->CR;
800918c: 687b ldr r3, [r7, #4]
800918e: 681b ldr r3, [r3, #0]
8009190: 60fb str r3, [r7, #12]
/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
8009192: 68fa ldr r2, [r7, #12]
8009194: 4b2a ldr r3, [pc, #168] (8009240 <DMA_Init+0xc4>)
8009196: ea02 0303 and.w r3, r2, r3
800919a: 60fb str r3, [r7, #12]
/* Set MSIZE bits according to DMA_MemoryDataSize value */
/* Set CIRC bit according to DMA_Mode value */
/* Set PL bits according to DMA_Priority value */
/* Set MBURST bits according to DMA_MemoryBurst value */
/* Set PBURST bits according to DMA_PeripheralBurst value */
tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
800919c: 683b ldr r3, [r7, #0]
800919e: 681a ldr r2, [r3, #0]
80091a0: 683b ldr r3, [r7, #0]
80091a2: 68db ldr r3, [r3, #12]
80091a4: ea42 0203 orr.w r2, r2, r3
80091a8: 683b ldr r3, [r7, #0]
80091aa: 695b ldr r3, [r3, #20]
80091ac: ea42 0203 orr.w r2, r2, r3
80091b0: 683b ldr r3, [r7, #0]
80091b2: 699b ldr r3, [r3, #24]
80091b4: ea42 0203 orr.w r2, r2, r3
80091b8: 683b ldr r3, [r7, #0]
80091ba: 69db ldr r3, [r3, #28]
80091bc: ea42 0203 orr.w r2, r2, r3
80091c0: 683b ldr r3, [r7, #0]
80091c2: 6a1b ldr r3, [r3, #32]
80091c4: ea42 0203 orr.w r2, r2, r3
80091c8: 683b ldr r3, [r7, #0]
80091ca: 6a5b ldr r3, [r3, #36]
80091cc: ea42 0203 orr.w r2, r2, r3
80091d0: 683b ldr r3, [r7, #0]
80091d2: 6a9b ldr r3, [r3, #40]
80091d4: ea42 0203 orr.w r2, r2, r3
80091d8: 683b ldr r3, [r7, #0]
80091da: 6b5b ldr r3, [r3, #52]
80091dc: ea42 0203 orr.w r2, r2, r3
80091e0: 683b ldr r3, [r7, #0]
80091e2: 6b9b ldr r3, [r3, #56]
80091e4: ea42 0203 orr.w r2, r2, r3
80091e8: 68fb ldr r3, [r7, #12]
80091ea: ea43 0302 orr.w r3, r3, r2
80091ee: 60fb str r3, [r7, #12]
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
/* Write to DMAy Streamx CR register */
DMAy_Streamx->CR = tmpreg;
80091f0: 687a ldr r2, [r7, #4]
80091f2: 68fb ldr r3, [r7, #12]
80091f4: 6013 str r3, [r2, #0]
/*------------------------- DMAy Streamx FCR Configuration -----------------*/
/* Get the DMAy_Streamx FCR value */
tmpreg = DMAy_Streamx->FCR;
80091f6: 687b ldr r3, [r7, #4]
80091f8: 695b ldr r3, [r3, #20]
80091fa: 60fb str r3, [r7, #12]
/* Clear DMDIS and FTH bits */
tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
80091fc: 68fb ldr r3, [r7, #12]
80091fe: f023 0307 bic.w r3, r3, #7 ; 0x7
8009202: 60fb str r3, [r7, #12]
/* Configure DMAy Streamx FIFO:
Set DMDIS bits according to DMA_FIFOMode value
Set FTH bits according to DMA_FIFOThreshold value */
tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
8009204: 683b ldr r3, [r7, #0]
8009206: 6ada ldr r2, [r3, #44]
8009208: 683b ldr r3, [r7, #0]
800920a: 6b1b ldr r3, [r3, #48]
800920c: ea42 0203 orr.w r2, r2, r3
8009210: 68fb ldr r3, [r7, #12]
8009212: ea43 0302 orr.w r3, r3, r2
8009216: 60fb str r3, [r7, #12]
/* Write to DMAy Streamx CR */
DMAy_Streamx->FCR = tmpreg;
8009218: 687a ldr r2, [r7, #4]
800921a: 68fb ldr r3, [r7, #12]
800921c: 6153 str r3, [r2, #20]
/*------------------------- DMAy Streamx NDTR Configuration ----------------*/
/* Write to DMAy Streamx NDTR register */
DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
800921e: 683b ldr r3, [r7, #0]
8009220: 691a ldr r2, [r3, #16]
8009222: 687b ldr r3, [r7, #4]
8009224: 605a str r2, [r3, #4]
/*------------------------- DMAy Streamx PAR Configuration -----------------*/
/* Write to DMAy Streamx PAR */
DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
8009226: 683b ldr r3, [r7, #0]
8009228: 685a ldr r2, [r3, #4]
800922a: 687b ldr r3, [r7, #4]
800922c: 609a str r2, [r3, #8]
/*------------------------- DMAy Streamx M0AR Configuration ----------------*/
/* Write to DMAy Streamx M0AR */
DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
800922e: 683b ldr r3, [r7, #0]
8009230: 689a ldr r2, [r3, #8]
8009232: 687b ldr r3, [r7, #4]
8009234: 60da str r2, [r3, #12]
}
8009236: f107 0714 add.w r7, r7, #20 ; 0x14
800923a: 46bd mov sp, r7
800923c: bc80 pop {r7}
800923e: 4770 bx lr
8009240: f01c803f .word 0xf01c803f
08009244 <DMA_StructInit>:
* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
{
8009244: b480 push {r7}
8009246: b083 sub sp, #12
8009248: af00 add r7, sp, #0
800924a: 6078 str r0, [r7, #4]
/*-------------- Reset DMA init structure parameters values ----------------*/
/* Initialize the DMA_Channel member */
DMA_InitStruct->DMA_Channel = 0;
800924c: 687a ldr r2, [r7, #4]
800924e: f04f 0300 mov.w r3, #0 ; 0x0
8009252: 6013 str r3, [r2, #0]
/* Initialize the DMA_PeripheralBaseAddr member */
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
8009254: 687a ldr r2, [r7, #4]
8009256: f04f 0300 mov.w r3, #0 ; 0x0
800925a: 6053 str r3, [r2, #4]
/* Initialize the DMA_Memory0BaseAddr member */
DMA_InitStruct->DMA_Memory0BaseAddr = 0;
800925c: 687a ldr r2, [r7, #4]
800925e: f04f 0300 mov.w r3, #0 ; 0x0
8009262: 6093 str r3, [r2, #8]
/* Initialize the DMA_DIR member */
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
8009264: 687a ldr r2, [r7, #4]
8009266: f04f 0300 mov.w r3, #0 ; 0x0
800926a: 60d3 str r3, [r2, #12]
/* Initialize the DMA_BufferSize member */
DMA_InitStruct->DMA_BufferSize = 0;
800926c: 687a ldr r2, [r7, #4]
800926e: f04f 0300 mov.w r3, #0 ; 0x0
8009272: 6113 str r3, [r2, #16]
/* Initialize the DMA_PeripheralInc member */
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
8009274: 687a ldr r2, [r7, #4]
8009276: f04f 0300 mov.w r3, #0 ; 0x0
800927a: 6153 str r3, [r2, #20]
/* Initialize the DMA_MemoryInc member */
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
800927c: 687a ldr r2, [r7, #4]
800927e: f04f 0300 mov.w r3, #0 ; 0x0
8009282: 6193 str r3, [r2, #24]
/* Initialize the DMA_PeripheralDataSize member */
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
8009284: 687a ldr r2, [r7, #4]
8009286: f04f 0300 mov.w r3, #0 ; 0x0
800928a: 61d3 str r3, [r2, #28]
/* Initialize the DMA_MemoryDataSize member */
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
800928c: 687a ldr r2, [r7, #4]
800928e: f04f 0300 mov.w r3, #0 ; 0x0
8009292: 6213 str r3, [r2, #32]
/* Initialize the DMA_Mode member */
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
8009294: 687a ldr r2, [r7, #4]
8009296: f04f 0300 mov.w r3, #0 ; 0x0
800929a: 6253 str r3, [r2, #36]
/* Initialize the DMA_Priority member */
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
800929c: 687a ldr r2, [r7, #4]
800929e: f04f 0300 mov.w r3, #0 ; 0x0
80092a2: 6293 str r3, [r2, #40]
/* Initialize the DMA_FIFOMode member */
DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
80092a4: 687a ldr r2, [r7, #4]
80092a6: f04f 0300 mov.w r3, #0 ; 0x0
80092aa: 62d3 str r3, [r2, #44]
/* Initialize the DMA_FIFOThreshold member */
DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
80092ac: 687a ldr r2, [r7, #4]
80092ae: f04f 0300 mov.w r3, #0 ; 0x0
80092b2: 6313 str r3, [r2, #48]
/* Initialize the DMA_MemoryBurst member */
DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
80092b4: 687a ldr r2, [r7, #4]
80092b6: f04f 0300 mov.w r3, #0 ; 0x0
80092ba: 6353 str r3, [r2, #52]
/* Initialize the DMA_PeripheralBurst member */
DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
80092bc: 687a ldr r2, [r7, #4]
80092be: f04f 0300 mov.w r3, #0 ; 0x0
80092c2: 6393 str r3, [r2, #56]
}
80092c4: f107 070c add.w r7, r7, #12 ; 0xc
80092c8: 46bd mov sp, r7
80092ca: bc80 pop {r7}
80092cc: 4770 bx lr
80092ce: 46c0 nop (mov r8, r8)
080092d0 <DMA_Cmd>:
* this single data is finished.
*
* @retval None
*/
void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
{
80092d0: b480 push {r7}
80092d2: b083 sub sp, #12
80092d4: af00 add r7, sp, #0
80092d6: 6078 str r0, [r7, #4]
80092d8: 460b mov r3, r1
80092da: 70fb strb r3, [r7, #3]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
//assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
80092dc: 78fb ldrb r3, [r7, #3]
80092de: 2b00 cmp r3, #0
80092e0: d006 beq.n 80092f0 <DMA_Cmd+0x20>
{
/* Enable the selected DMAy Streamx by setting EN bit */
DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN;
80092e2: 687b ldr r3, [r7, #4]
80092e4: 681b ldr r3, [r3, #0]
80092e6: f043 0201 orr.w r2, r3, #1 ; 0x1
80092ea: 687b ldr r3, [r7, #4]
80092ec: 601a str r2, [r3, #0]
80092ee: e005 b.n 80092fc <DMA_Cmd+0x2c>
}
else
{
/* Disable the selected DMAy Streamx by clearing EN bit */
DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN;
80092f0: 687b ldr r3, [r7, #4]
80092f2: 681b ldr r3, [r3, #0]
80092f4: f023 0201 bic.w r2, r3, #1 ; 0x1
80092f8: 687b ldr r3, [r7, #4]
80092fa: 601a str r2, [r3, #0]
}
}
80092fc: f107 070c add.w r7, r7, #12 ; 0xc
8009300: 46bd mov sp, r7
8009302: bc80 pop {r7}
8009304: 4770 bx lr
8009306: 46c0 nop (mov r8, r8)
08009308 <DMA_PeriphIncOffsetSizeConfig>:
* @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is
* fixed to 4 (32-bit aligned addresses).
* @retval None
*/
void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos)
{
8009308: b480 push {r7}
800930a: b083 sub sp, #12
800930c: af00 add r7, sp, #0
800930e: 6078 str r0, [r7, #4]
8009310: 6039 str r1, [r7, #0]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
//assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
/* Check the needed Peripheral increment offset */
if(DMA_Pincos != DMA_PINCOS_Psize)
8009312: 683b ldr r3, [r7, #0]
8009314: 2b00 cmp r3, #0
8009316: d006 beq.n 8009326 <DMA_PeriphIncOffsetSizeConfig+0x1e>
{
/* Configure DMA_SxCR_PINCOS bit with the input parameter */
DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS;
8009318: 687b ldr r3, [r7, #4]
800931a: 681b ldr r3, [r3, #0]
800931c: f443 4200 orr.w r2, r3, #32768 ; 0x8000
8009320: 687b ldr r3, [r7, #4]
8009322: 601a str r2, [r3, #0]
8009324: e005 b.n 8009332 <DMA_PeriphIncOffsetSizeConfig+0x2a>
}
else
{
/* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS;
8009326: 687b ldr r3, [r7, #4]
8009328: 681b ldr r3, [r3, #0]
800932a: f423 4200 bic.w r2, r3, #32768 ; 0x8000
800932e: 687b ldr r3, [r7, #4]
8009330: 601a str r2, [r3, #0]
}
}
8009332: f107 070c add.w r7, r7, #12 ; 0xc
8009336: 46bd mov sp, r7
8009338: bc80 pop {r7}
800933a: 4770 bx lr
0800933c <DMA_FlowControllerConfig>:
* @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller
* is the peripheral.
* @retval None
*/
void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl)
{
800933c: b480 push {r7}
800933e: b083 sub sp, #12
8009340: af00 add r7, sp, #0
8009342: 6078 str r0, [r7, #4]
8009344: 6039 str r1, [r7, #0]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
//assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
/* Check the needed flow controller */
if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
8009346: 683b ldr r3, [r7, #0]
8009348: 2b00 cmp r3, #0
800934a: d006 beq.n 800935a <DMA_FlowControllerConfig+0x1e>
{
/* Configure DMA_SxCR_PFCTRL bit with the input parameter */
DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL;
800934c: 687b ldr r3, [r7, #4]
800934e: 681b ldr r3, [r3, #0]
8009350: f043 0220 orr.w r2, r3, #32 ; 0x20
8009354: 687b ldr r3, [r7, #4]
8009356: 601a str r2, [r3, #0]
8009358: e005 b.n 8009366 <DMA_FlowControllerConfig+0x2a>
}
else
{
/* Clear the PFCTRL bit: Memory is the flow controller */
DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL;
800935a: 687b ldr r3, [r7, #4]
800935c: 681b ldr r3, [r3, #0]
800935e: f023 0220 bic.w r2, r3, #32 ; 0x20
8009362: 687b ldr r3, [r7, #4]
8009364: 601a str r2, [r3, #0]
}
}
8009366: f107 070c add.w r7, r7, #12 ; 0xc
800936a: 46bd mov sp, r7
800936c: bc80 pop {r7}
800936e: 4770 bx lr
08009370 <DMA_SetCurrDataCounter>:
* DMAy_SxPAR register is considered as Peripheral.
*
* @retval The number of remaining data units in the current DMAy Streamx transfer.
*/
void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)
{
8009370: b480 push {r7}
8009372: b083 sub sp, #12
8009374: af00 add r7, sp, #0
8009376: 6078 str r0, [r7, #4]
8009378: 460b mov r3, r1
800937a: 807b strh r3, [r7, #2]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
/* Write the number of data units to be transferred */
DMAy_Streamx->NDTR = (uint16_t)Counter;
800937c: 887a ldrh r2, [r7, #2]
800937e: 687b ldr r3, [r7, #4]
8009380: 605a str r2, [r3, #4]
}
8009382: f107 070c add.w r7, r7, #12 ; 0xc
8009386: 46bd mov sp, r7
8009388: bc80 pop {r7}
800938a: 4770 bx lr
0800938c <DMA_GetCurrDataCounter>:
* @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
* to 7 to select the DMA Stream.
* @retval The number of remaining data units in the current DMAy Streamx transfer.
*/
uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)
{
800938c: b480 push {r7}
800938e: b083 sub sp, #12
8009390: af00 add r7, sp, #0
8009392: 6078 str r0, [r7, #4]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
/* Return the number of remaining data units for DMAy Streamx */
return ((uint16_t)(DMAy_Streamx->NDTR));
8009394: 687b ldr r3, [r7, #4]
8009396: 685b ldr r3, [r3, #4]
8009398: b29b uxth r3, r3
}
800939a: 4618 mov r0, r3
800939c: f107 070c add.w r7, r7, #12 ; 0xc
80093a0: 46bd mov sp, r7
80093a2: bc80 pop {r7}
80093a4: 4770 bx lr
80093a6: 46c0 nop (mov r8, r8)
080093a8 <DMA_DoubleBufferModeConfig>:
*
* @retval None
*/
void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
uint32_t DMA_CurrentMemory)
{
80093a8: b480 push {r7}
80093aa: b085 sub sp, #20
80093ac: af00 add r7, sp, #0
80093ae: 60f8 str r0, [r7, #12]
80093b0: 60b9 str r1, [r7, #8]
80093b2: 607a str r2, [r7, #4]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
//assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
if (DMA_CurrentMemory != DMA_Memory_0)
80093b4: 687b ldr r3, [r7, #4]
80093b6: 2b00 cmp r3, #0
80093b8: d006 beq.n 80093c8 <DMA_DoubleBufferModeConfig+0x20>
{
/* Set Memory 1 as current memory address */
DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT);
80093ba: 68fb ldr r3, [r7, #12]
80093bc: 681b ldr r3, [r3, #0]
80093be: f443 2200 orr.w r2, r3, #524288 ; 0x80000
80093c2: 68fb ldr r3, [r7, #12]
80093c4: 601a str r2, [r3, #0]
80093c6: e005 b.n 80093d4 <DMA_DoubleBufferModeConfig+0x2c>
}
else
{
/* Set Memory 0 as current memory address */
DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT);
80093c8: 68fb ldr r3, [r7, #12]
80093ca: 681b ldr r3, [r3, #0]
80093cc: f423 2200 bic.w r2, r3, #524288 ; 0x80000
80093d0: 68fb ldr r3, [r7, #12]
80093d2: 601a str r2, [r3, #0]
}
/* Write to DMAy Streamx M1AR */
DMAy_Streamx->M1AR = Memory1BaseAddr;
80093d4: 68fa ldr r2, [r7, #12]
80093d6: 68bb ldr r3, [r7, #8]
80093d8: 6113 str r3, [r2, #16]
}
80093da: f107 0714 add.w r7, r7, #20 ; 0x14
80093de: 46bd mov sp, r7
80093e0: bc80 pop {r7}
80093e2: 4770 bx lr
080093e4 <DMA_DoubleBufferModeCmd>:
* @param NewState: new state of the DMAy Streamx double buffer mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
{
80093e4: b480 push {r7}
80093e6: b083 sub sp, #12
80093e8: af00 add r7, sp, #0
80093ea: 6078 str r0, [r7, #4]
80093ec: 460b mov r3, r1
80093ee: 70fb strb r3, [r7, #3]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
//assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Configure the Double Buffer mode */
if (NewState != DISABLE)
80093f0: 78fb ldrb r3, [r7, #3]
80093f2: 2b00 cmp r3, #0
80093f4: d006 beq.n 8009404 <DMA_DoubleBufferModeCmd+0x20>
{
/* Enable the Double buffer mode */
DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM;
80093f6: 687b ldr r3, [r7, #4]
80093f8: 681b ldr r3, [r3, #0]
80093fa: f443 2280 orr.w r2, r3, #262144 ; 0x40000
80093fe: 687b ldr r3, [r7, #4]
8009400: 601a str r2, [r3, #0]
8009402: e005 b.n 8009410 <DMA_DoubleBufferModeCmd+0x2c>
}
else
{
/* Disable the Double buffer mode */
DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM;
8009404: 687b ldr r3, [r7, #4]
8009406: 681b ldr r3, [r3, #0]
8009408: f423 2280 bic.w r2, r3, #262144 ; 0x40000
800940c: 687b ldr r3, [r7, #4]
800940e: 601a str r2, [r3, #0]
}
}
8009410: f107 070c add.w r7, r7, #12 ; 0xc
8009414: 46bd mov sp, r7
8009416: bc80 pop {r7}
8009418: 4770 bx lr
800941a: 46c0 nop (mov r8, r8)
0800941c <DMA_MemoryTargetConfig>:
*
* @retval None
*/
void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
uint32_t DMA_MemoryTarget)
{
800941c: b480 push {r7}
800941e: b085 sub sp, #20
8009420: af00 add r7, sp, #0
8009422: 60f8 str r0, [r7, #12]
8009424: 60b9 str r1, [r7, #8]
8009426: 607a str r2, [r7, #4]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
//assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
/* Check the Memory target to be configured */
if (DMA_MemoryTarget != DMA_Memory_0)
8009428: 687b ldr r3, [r7, #4]
800942a: 2b00 cmp r3, #0
800942c: d003 beq.n 8009436 <DMA_MemoryTargetConfig+0x1a>
{
/* Write to DMAy Streamx M1AR */
DMAy_Streamx->M1AR = MemoryBaseAddr;
800942e: 68fa ldr r2, [r7, #12]
8009430: 68bb ldr r3, [r7, #8]
8009432: 6113 str r3, [r2, #16]
8009434: e002 b.n 800943c <DMA_MemoryTargetConfig+0x20>
}
else
{
/* Write to DMAy Streamx M0AR */
DMAy_Streamx->M0AR = MemoryBaseAddr;
8009436: 68fa ldr r2, [r7, #12]
8009438: 68bb ldr r3, [r7, #8]
800943a: 60d3 str r3, [r2, #12]
}
}
800943c: f107 0714 add.w r7, r7, #20 ; 0x14
8009440: 46bd mov sp, r7
8009442: bc80 pop {r7}
8009444: 4770 bx lr
8009446: 46c0 nop (mov r8, r8)
08009448 <DMA_GetCurrentMemoryTarget>:
* @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
* to 7 to select the DMA Stream.
* @retval The memory target number: 0 for Memory0 or 1 for Memory1.
*/
uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx)
{
8009448: b480 push {r7}
800944a: b085 sub sp, #20
800944c: af00 add r7, sp, #0
800944e: 6078 str r0, [r7, #4]
uint32_t tmp = 0;
8009450: f04f 0300 mov.w r3, #0 ; 0x0
8009454: 60fb str r3, [r7, #12]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
/* Get the current memory target */
if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0)
8009456: 687b ldr r3, [r7, #4]
8009458: 681b ldr r3, [r3, #0]
800945a: f403 2300 and.w r3, r3, #524288 ; 0x80000
800945e: 2b00 cmp r3, #0
8009460: d003 beq.n 800946a <DMA_GetCurrentMemoryTarget+0x22>
{
/* Current memory buffer used is Memory 1 */
tmp = 1;
8009462: f04f 0301 mov.w r3, #1 ; 0x1
8009466: 60fb str r3, [r7, #12]
8009468: e002 b.n 8009470 <DMA_GetCurrentMemoryTarget+0x28>
}
else
{
/* Current memory buffer used is Memory 0 */
tmp = 0;
800946a: f04f 0300 mov.w r3, #0 ; 0x0
800946e: 60fb str r3, [r7, #12]
}
return tmp;
8009470: 68fb ldr r3, [r7, #12]
}
8009472: 4618 mov r0, r3
8009474: f107 0714 add.w r7, r7, #20 ; 0x14
8009478: 46bd mov sp, r7
800947a: bc80 pop {r7}
800947c: 4770 bx lr
800947e: 46c0 nop (mov r8, r8)
08009480 <DMA_GetCmdStatus>:
* of this single data is finished.
*
* @retval Current state of the DMAy Streamx (ENABLE or DISABLE).
*/
FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx)
{
8009480: b480 push {r7}
8009482: b085 sub sp, #20
8009484: af00 add r7, sp, #0
8009486: 6078 str r0, [r7, #4]
FunctionalState state = DISABLE;
8009488: f04f 0300 mov.w r3, #0 ; 0x0
800948c: 73fb strb r3, [r7, #15]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0)
800948e: 687b ldr r3, [r7, #4]
8009490: 681b ldr r3, [r3, #0]
8009492: f003 0301 and.w r3, r3, #1 ; 0x1
8009496: b2db uxtb r3, r3
8009498: 2b00 cmp r3, #0
800949a: d003 beq.n 80094a4 <DMA_GetCmdStatus+0x24>
{
/* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
state = ENABLE;
800949c: f04f 0301 mov.w r3, #1 ; 0x1
80094a0: 73fb strb r3, [r7, #15]
80094a2: e002 b.n 80094aa <DMA_GetCmdStatus+0x2a>
}
else
{
/* The selected DMAy Streamx EN bit is cleared (DMA is disabled and
all transfers are complete) */
state = DISABLE;
80094a4: f04f 0300 mov.w r3, #0 ; 0x0
80094a8: 73fb strb r3, [r7, #15]
}
return state;
80094aa: 7bfb ldrb r3, [r7, #15]
}
80094ac: 4618 mov r0, r3
80094ae: f107 0714 add.w r7, r7, #20 ; 0x14
80094b2: 46bd mov sp, r7
80094b4: bc80 pop {r7}
80094b6: 4770 bx lr
080094b8 <DMA_GetFIFOStatus>:
* - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
* - DMA_FIFOStatus_Empty: when FIFO is empty
* - DMA_FIFOStatus_Full: when FIFO is full
*/
uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)
{
80094b8: b480 push {r7}
80094ba: b085 sub sp, #20
80094bc: af00 add r7, sp, #0
80094be: 6078 str r0, [r7, #4]
uint32_t tmpreg = 0;
80094c0: f04f 0300 mov.w r3, #0 ; 0x0
80094c4: 60fb str r3, [r7, #12]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
/* Get the FIFO level bits */
tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));
80094c6: 687b ldr r3, [r7, #4]
80094c8: 695b ldr r3, [r3, #20]
80094ca: f003 0338 and.w r3, r3, #56 ; 0x38
80094ce: 60fb str r3, [r7, #12]
return tmpreg;
80094d0: 68fb ldr r3, [r7, #12]
}
80094d2: 4618 mov r0, r3
80094d4: f107 0714 add.w r7, r7, #20 ; 0x14
80094d8: 46bd mov sp, r7
80094da: bc80 pop {r7}
80094dc: 4770 bx lr
80094de: 46c0 nop (mov r8, r8)
080094e0 <DMA_GetFlagStatus>:
* @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
* Where x can be 0 to 7 to select the DMA Stream.
* @retval The new state of DMA_FLAG (SET or RESET).
*/
FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
{
80094e0: b480 push {r7}
80094e2: b087 sub sp, #28
80094e4: af00 add r7, sp, #0
80094e6: 6078 str r0, [r7, #4]
80094e8: 6039 str r1, [r7, #0]
FlagStatus bitstatus = RESET;
80094ea: f04f 0300 mov.w r3, #0 ; 0x0
80094ee: 73fb strb r3, [r7, #15]
DMA_TypeDef* DMAy;
uint32_t tmpreg = 0;
80094f0: f04f 0300 mov.w r3, #0 ; 0x0
80094f4: 617b str r3, [r7, #20]
/* Check the parameters */
//assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
//assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
/* Determine the DMA to which belongs the stream */
if (DMAy_Streamx < DMA2_Stream0)
80094f6: 687a ldr r2, [r7, #4]
80094f8: 4b16 ldr r3, [pc, #88] (8009554 <DMA_GetFlagStatus+0x74>)
80094fa: 429a cmp r2, r3
80094fc: d802 bhi.n 8009504 <DMA_GetFlagStatus+0x24>
{
/* DMAy_Streamx belongs to DMA1 */
DMAy = DMA1;
80094fe: 4b16 ldr r3, [pc, #88] (8009558 <DMA_GetFlagStatus+0x78>)
8009500: 613b str r3, [r7, #16]
8009502: e001 b.n 8009508 <DMA_GetFlagStatus+0x28>