main.list

  } 
  else 
  {
    /* DMAy_Streamx belongs to DMA2 */
    DMAy = DMA2; 
 8009504:	4b15      	ldr	r3, [pc, #84]	(800955c <DMA_GetFlagStatus+0x7c>)
 8009506:	613b      	str	r3, [r7, #16]
  }

  /* Check if the flag is in HISR or LISR */
  if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
 8009508:	683b      	ldr	r3, [r7, #0]
 800950a:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
 800950e:	2b00      	cmp	r3, #0
 8009510:	d003      	beq.n	800951a <DMA_GetFlagStatus+0x3a>
  {
    /* Get DMAy HISR register value */
    tmpreg = DMAy->HISR;
 8009512:	693b      	ldr	r3, [r7, #16]
 8009514:	685b      	ldr	r3, [r3, #4]
 8009516:	617b      	str	r3, [r7, #20]
 8009518:	e002      	b.n	8009520 <DMA_GetFlagStatus+0x40>
  }
  else
  {
    /* Get DMAy LISR register value */
    tmpreg = DMAy->LISR;
 800951a:	693b      	ldr	r3, [r7, #16]
 800951c:	681b      	ldr	r3, [r3, #0]
 800951e:	617b      	str	r3, [r7, #20]
  }   
 
  /* Mask the reserved bits */
  tmpreg &= (uint32_t)RESERVED_MASK;
 8009520:	697a      	ldr	r2, [r7, #20]
 8009522:	4b0f      	ldr	r3, [pc, #60]	(8009560 <DMA_GetFlagStatus+0x80>)
 8009524:	ea02 0303 	and.w	r3, r2, r3
 8009528:	617b      	str	r3, [r7, #20]

  /* Check the status of the specified DMA flag */
  if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
 800952a:	697a      	ldr	r2, [r7, #20]
 800952c:	683b      	ldr	r3, [r7, #0]
 800952e:	ea02 0303 	and.w	r3, r2, r3
 8009532:	2b00      	cmp	r3, #0
 8009534:	d003      	beq.n	800953e <DMA_GetFlagStatus+0x5e>
  {
    /* DMA_FLAG is set */
    bitstatus = SET;
 8009536:	f04f 0301 	mov.w	r3, #1	; 0x1
 800953a:	73fb      	strb	r3, [r7, #15]
 800953c:	e002      	b.n	8009544 <DMA_GetFlagStatus+0x64>
  }
  else
  {
    /* DMA_FLAG is reset */
    bitstatus = RESET;
 800953e:	f04f 0300 	mov.w	r3, #0	; 0x0
 8009542:	73fb      	strb	r3, [r7, #15]
  }

  /* Return the DMA_FLAG status */
  return  bitstatus;
 8009544:	7bfb      	ldrb	r3, [r7, #15]
}
 8009546:	4618      	mov	r0, r3
 8009548:	f107 071c 	add.w	r7, r7, #28	; 0x1c
 800954c:	46bd      	mov	sp, r7
 800954e:	bc80      	pop	{r7}
 8009550:	4770      	bx	lr
 8009552:	46c0      	nop			(mov r8, r8)
 8009554:	4002640f 	.word	0x4002640f
 8009558:	40026000 	.word	0x40026000
 800955c:	40026400 	.word	0x40026400
 8009560:	0f7d0f7d 	.word	0x0f7d0f7d

08009564 <DMA_ClearFlag>:
  *            @arg DMA_FLAG_FEIFx:  Streamx FIFO error flag
  *         Where x can be 0 to 7 to select the DMA Stream.   
  * @retval None
  */
void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
{
 8009564:	b480      	push	{r7}
 8009566:	b085      	sub	sp, #20
 8009568:	af00      	add	r7, sp, #0
 800956a:	6078      	str	r0, [r7, #4]
 800956c:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  //assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
  //assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));

  /* Determine the DMA to which belongs the stream */
  if (DMAy_Streamx < DMA2_Stream0)
 800956e:	687a      	ldr	r2, [r7, #4]
 8009570:	4b0f      	ldr	r3, [pc, #60]	(80095b0 <DMA_ClearFlag+0x4c>)
 8009572:	429a      	cmp	r2, r3
 8009574:	d802      	bhi.n	800957c <DMA_ClearFlag+0x18>
  {
    /* DMAy_Streamx belongs to DMA1 */
    DMAy = DMA1; 
 8009576:	4b0f      	ldr	r3, [pc, #60]	(80095b4 <DMA_ClearFlag+0x50>)
 8009578:	60fb      	str	r3, [r7, #12]
 800957a:	e001      	b.n	8009580 <DMA_ClearFlag+0x1c>
  } 
  else 
  {
    /* DMAy_Streamx belongs to DMA2 */
    DMAy = DMA2; 
 800957c:	4b0e      	ldr	r3, [pc, #56]	(80095b8 <DMA_ClearFlag+0x54>)
 800957e:	60fb      	str	r3, [r7, #12]
  }

  /* Check if LIFCR or HIFCR register is targeted */
  if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
 8009580:	683b      	ldr	r3, [r7, #0]
 8009582:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
 8009586:	2b00      	cmp	r3, #0
 8009588:	d006      	beq.n	8009598 <DMA_ClearFlag+0x34>
  {
    /* Set DMAy HIFCR register clear flag bits */
    DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
 800958a:	683b      	ldr	r3, [r7, #0]
 800958c:	4a0b      	ldr	r2, [pc, #44]	(80095bc <DMA_ClearFlag+0x58>)
 800958e:	ea03 0202 	and.w	r2, r3, r2
 8009592:	68fb      	ldr	r3, [r7, #12]
 8009594:	60da      	str	r2, [r3, #12]
 8009596:	e005      	b.n	80095a4 <DMA_ClearFlag+0x40>
  }
  else 
  {
    /* Set DMAy LIFCR register clear flag bits */
    DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
 8009598:	683b      	ldr	r3, [r7, #0]
 800959a:	4a08      	ldr	r2, [pc, #32]	(80095bc <DMA_ClearFlag+0x58>)
 800959c:	ea03 0202 	and.w	r2, r3, r2
 80095a0:	68fb      	ldr	r3, [r7, #12]
 80095a2:	609a      	str	r2, [r3, #8]
  }    
}
 80095a4:	f107 0714 	add.w	r7, r7, #20	; 0x14
 80095a8:	46bd      	mov	sp, r7
 80095aa:	bc80      	pop	{r7}
 80095ac:	4770      	bx	lr
 80095ae:	46c0      	nop			(mov r8, r8)
 80095b0:	4002640f 	.word	0x4002640f
 80095b4:	40026000 	.word	0x40026000
 80095b8:	40026400 	.word	0x40026400
 80095bc:	0f7d0f7d 	.word	0x0f7d0f7d

080095c0 <DMA_ITConfig>:
  * @param  NewState: new state of the specified DMA interrupts.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
{
 80095c0:	b480      	push	{r7}
 80095c2:	b085      	sub	sp, #20
 80095c4:	af00      	add	r7, sp, #0
 80095c6:	60f8      	str	r0, [r7, #12]
 80095c8:	60b9      	str	r1, [r7, #8]
 80095ca:	4613      	mov	r3, r2
 80095cc:	71fb      	strb	r3, [r7, #7]
  //assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
  //assert_param(IS_DMA_CONFIG_IT(DMA_IT));
  //assert_param(IS_FUNCTIONAL_STATE(NewState));

  /* Check if the DMA_IT parameter contains a FIFO interrupt */
  if ((DMA_IT & DMA_IT_FE) != 0)
 80095ce:	68bb      	ldr	r3, [r7, #8]
 80095d0:	f003 0380 	and.w	r3, r3, #128	; 0x80
 80095d4:	2b00      	cmp	r3, #0
 80095d6:	d00f      	beq.n	80095f8 <DMA_ITConfig+0x38>
  {
    if (NewState != DISABLE)
 80095d8:	79fb      	ldrb	r3, [r7, #7]
 80095da:	2b00      	cmp	r3, #0
 80095dc:	d006      	beq.n	80095ec <DMA_ITConfig+0x2c>
    {
      /* Enable the selected DMA FIFO interrupts */
      DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE;
 80095de:	68fb      	ldr	r3, [r7, #12]
 80095e0:	695b      	ldr	r3, [r3, #20]
 80095e2:	f043 0280 	orr.w	r2, r3, #128	; 0x80
 80095e6:	68fb      	ldr	r3, [r7, #12]
 80095e8:	615a      	str	r2, [r3, #20]
 80095ea:	e005      	b.n	80095f8 <DMA_ITConfig+0x38>
    }    
    else 
    {
      /* Disable the selected DMA FIFO interrupts */
      DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE;  
 80095ec:	68fb      	ldr	r3, [r7, #12]
 80095ee:	695b      	ldr	r3, [r3, #20]
 80095f0:	f023 0280 	bic.w	r2, r3, #128	; 0x80
 80095f4:	68fb      	ldr	r3, [r7, #12]
 80095f6:	615a      	str	r2, [r3, #20]
    }
  }

  /* Check if the DMA_IT parameter contains a Transfer interrupt */
  if (DMA_IT != DMA_IT_FE)
 80095f8:	68bb      	ldr	r3, [r7, #8]
 80095fa:	2b80      	cmp	r3, #128
 80095fc:	d017      	beq.n	800962e <DMA_ITConfig+0x6e>
  {
    if (NewState != DISABLE)
 80095fe:	79fb      	ldrb	r3, [r7, #7]
 8009600:	2b00      	cmp	r3, #0
 8009602:	d009      	beq.n	8009618 <DMA_ITConfig+0x58>
    {
      /* Enable the selected DMA transfer interrupts */
      DMAy_Streamx->CR |= (uint32_t)(DMA_IT  & TRANSFER_IT_ENABLE_MASK);
 8009604:	68fb      	ldr	r3, [r7, #12]
 8009606:	681a      	ldr	r2, [r3, #0]
 8009608:	68bb      	ldr	r3, [r7, #8]
 800960a:	f003 031e 	and.w	r3, r3, #30	; 0x1e
 800960e:	ea42 0203 	orr.w	r2, r2, r3
 8009612:	68fb      	ldr	r3, [r7, #12]
 8009614:	601a      	str	r2, [r3, #0]
 8009616:	e00a      	b.n	800962e <DMA_ITConfig+0x6e>
    }
    else
    {
      /* Disable the selected DMA transfer interrupts */
      DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
 8009618:	68fb      	ldr	r3, [r7, #12]
 800961a:	681a      	ldr	r2, [r3, #0]
 800961c:	68bb      	ldr	r3, [r7, #8]
 800961e:	f003 031e 	and.w	r3, r3, #30	; 0x1e
 8009622:	ea6f 0303 	mvn.w	r3, r3
 8009626:	ea02 0203 	and.w	r2, r2, r3
 800962a:	68fb      	ldr	r3, [r7, #12]
 800962c:	601a      	str	r2, [r3, #0]
    }    
  }
}
 800962e:	f107 0714 	add.w	r7, r7, #20	; 0x14
 8009632:	46bd      	mov	sp, r7
 8009634:	bc80      	pop	{r7}
 8009636:	4770      	bx	lr

08009638 <DMA_GetITStatus>:
  *            @arg DMA_IT_FEIFx:  Streamx FIFO error interrupt
  *         Where x can be 0 to 7 to select the DMA Stream.
  * @retval The new state of DMA_IT (SET or RESET).
  */
ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
{
 8009638:	b480      	push	{r7}
 800963a:	b087      	sub	sp, #28
 800963c:	af00      	add	r7, sp, #0
 800963e:	6078      	str	r0, [r7, #4]
 8009640:	6039      	str	r1, [r7, #0]
  ITStatus bitstatus = RESET;
 8009642:	f04f 0300 	mov.w	r3, #0	; 0x0
 8009646:	72fb      	strb	r3, [r7, #11]
  DMA_TypeDef* DMAy;
  uint32_t tmpreg = 0, enablestatus = 0;
 8009648:	f04f 0300 	mov.w	r3, #0	; 0x0
 800964c:	613b      	str	r3, [r7, #16]
 800964e:	f04f 0300 	mov.w	r3, #0	; 0x0
 8009652:	617b      	str	r3, [r7, #20]
  /* Check the parameters */
  //assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
  //assert_param(IS_DMA_GET_IT(DMA_IT));
 
  /* Determine the DMA to which belongs the stream */
  if (DMAy_Streamx < DMA2_Stream0)
 8009654:	687a      	ldr	r2, [r7, #4]
 8009656:	4b24      	ldr	r3, [pc, #144]	(80096e8 <DMA_GetITStatus+0xb0>)
 8009658:	429a      	cmp	r2, r3
 800965a:	d802      	bhi.n	8009662 <DMA_GetITStatus+0x2a>
  {
    /* DMAy_Streamx belongs to DMA1 */
    DMAy = DMA1; 
 800965c:	4b23      	ldr	r3, [pc, #140]	(80096ec <DMA_GetITStatus+0xb4>)
 800965e:	60fb      	str	r3, [r7, #12]
 8009660:	e001      	b.n	8009666 <DMA_GetITStatus+0x2e>
  } 
  else 
  {
    /* DMAy_Streamx belongs to DMA2 */
    DMAy = DMA2; 
 8009662:	4b23      	ldr	r3, [pc, #140]	(80096f0 <DMA_GetITStatus+0xb8>)
 8009664:	60fb      	str	r3, [r7, #12]
  }

  /* Check if the interrupt enable bit is in the CR or FCR register */
  if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
 8009666:	683a      	ldr	r2, [r7, #0]
 8009668:	4b22      	ldr	r3, [pc, #136]	(80096f4 <DMA_GetITStatus+0xbc>)
 800966a:	ea02 0303 	and.w	r3, r2, r3
 800966e:	2b00      	cmp	r3, #0
 8009670:	d00c      	beq.n	800968c <DMA_GetITStatus+0x54>
  {
    /* Get the interrupt enable position mask in CR register */
    tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);   
 8009672:	683b      	ldr	r3, [r7, #0]
 8009674:	ea4f 23d3 	mov.w	r3, r3, lsr #11
 8009678:	f003 031e 	and.w	r3, r3, #30	; 0x1e
 800967c:	613b      	str	r3, [r7, #16]
    
    /* Check the enable bit in CR register */
    enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
 800967e:	687b      	ldr	r3, [r7, #4]
 8009680:	681a      	ldr	r2, [r3, #0]
 8009682:	693b      	ldr	r3, [r7, #16]
 8009684:	ea02 0303 	and.w	r3, r2, r3
 8009688:	617b      	str	r3, [r7, #20]
 800968a:	e004      	b.n	8009696 <DMA_GetITStatus+0x5e>
  }
  else 
  {
    /* Check the enable bit in FCR register */
    enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); 
 800968c:	687b      	ldr	r3, [r7, #4]
 800968e:	695b      	ldr	r3, [r3, #20]
 8009690:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8009694:	617b      	str	r3, [r7, #20]
  }
 
  /* Check if the interrupt pending flag is in LISR or HISR */
  if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
 8009696:	683b      	ldr	r3, [r7, #0]
 8009698:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
 800969c:	2b00      	cmp	r3, #0
 800969e:	d003      	beq.n	80096a8 <DMA_GetITStatus+0x70>
  {
    /* Get DMAy HISR register value */
    tmpreg = DMAy->HISR ;
 80096a0:	68fb      	ldr	r3, [r7, #12]
 80096a2:	685b      	ldr	r3, [r3, #4]
 80096a4:	613b      	str	r3, [r7, #16]
 80096a6:	e002      	b.n	80096ae <DMA_GetITStatus+0x76>
  }
  else
  {
    /* Get DMAy LISR register value */
    tmpreg = DMAy->LISR ;
 80096a8:	68fb      	ldr	r3, [r7, #12]
 80096aa:	681b      	ldr	r3, [r3, #0]
 80096ac:	613b      	str	r3, [r7, #16]
  } 

  /* mask all reserved bits */
  tmpreg &= (uint32_t)RESERVED_MASK;
 80096ae:	693a      	ldr	r2, [r7, #16]
 80096b0:	4b11      	ldr	r3, [pc, #68]	(80096f8 <DMA_GetITStatus+0xc0>)
 80096b2:	ea02 0303 	and.w	r3, r2, r3
 80096b6:	613b      	str	r3, [r7, #16]

  /* Check the status of the specified DMA interrupt */
  if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 80096b8:	693a      	ldr	r2, [r7, #16]
 80096ba:	683b      	ldr	r3, [r7, #0]
 80096bc:	ea02 0303 	and.w	r3, r2, r3
 80096c0:	2b00      	cmp	r3, #0
 80096c2:	d006      	beq.n	80096d2 <DMA_GetITStatus+0x9a>
 80096c4:	697b      	ldr	r3, [r7, #20]
 80096c6:	2b00      	cmp	r3, #0
 80096c8:	d003      	beq.n	80096d2 <DMA_GetITStatus+0x9a>
  {
    /* DMA_IT is set */
    bitstatus = SET;
 80096ca:	f04f 0301 	mov.w	r3, #1	; 0x1
 80096ce:	72fb      	strb	r3, [r7, #11]
 80096d0:	e002      	b.n	80096d8 <DMA_GetITStatus+0xa0>
  }
  else
  {
    /* DMA_IT is reset */
    bitstatus = RESET;
 80096d2:	f04f 0300 	mov.w	r3, #0	; 0x0
 80096d6:	72fb      	strb	r3, [r7, #11]
  }

  /* Return the DMA_IT status */
  return  bitstatus;
 80096d8:	7afb      	ldrb	r3, [r7, #11]
}
 80096da:	4618      	mov	r0, r3
 80096dc:	f107 071c 	add.w	r7, r7, #28	; 0x1c
 80096e0:	46bd      	mov	sp, r7
 80096e2:	bc80      	pop	{r7}
 80096e4:	4770      	bx	lr
 80096e6:	46c0      	nop			(mov r8, r8)
 80096e8:	4002640f 	.word	0x4002640f
 80096ec:	40026000 	.word	0x40026000
 80096f0:	40026400 	.word	0x40026400
 80096f4:	0f3c0f3c 	.word	0x0f3c0f3c
 80096f8:	0f7d0f7d 	.word	0x0f7d0f7d

080096fc <DMA_ClearITPendingBit>:
  *            @arg DMA_IT_FEIFx:  Streamx FIFO error interrupt
  *         Where x can be 0 to 7 to select the DMA Stream.
  * @retval None
  */
void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
{
 80096fc:	b480      	push	{r7}
 80096fe:	b085      	sub	sp, #20
 8009700:	af00      	add	r7, sp, #0
 8009702:	6078      	str	r0, [r7, #4]
 8009704:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  //assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
  //assert_param(IS_DMA_CLEAR_IT(DMA_IT));

  /* Determine the DMA to which belongs the stream */
  if (DMAy_Streamx < DMA2_Stream0)
 8009706:	687a      	ldr	r2, [r7, #4]
 8009708:	4b0f      	ldr	r3, [pc, #60]	(8009748 <DMA_ClearITPendingBit+0x4c>)
 800970a:	429a      	cmp	r2, r3
 800970c:	d802      	bhi.n	8009714 <DMA_ClearITPendingBit+0x18>
  {
    /* DMAy_Streamx belongs to DMA1 */
    DMAy = DMA1; 
 800970e:	4b0f      	ldr	r3, [pc, #60]	(800974c <DMA_ClearITPendingBit+0x50>)
 8009710:	60fb      	str	r3, [r7, #12]
 8009712:	e001      	b.n	8009718 <DMA_ClearITPendingBit+0x1c>
  } 
  else 
  {
    /* DMAy_Streamx belongs to DMA2 */
    DMAy = DMA2; 
 8009714:	4b0e      	ldr	r3, [pc, #56]	(8009750 <DMA_ClearITPendingBit+0x54>)
 8009716:	60fb      	str	r3, [r7, #12]
  }

  /* Check if LIFCR or HIFCR register is targeted */
  if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
 8009718:	683b      	ldr	r3, [r7, #0]
 800971a:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
 800971e:	2b00      	cmp	r3, #0
 8009720:	d006      	beq.n	8009730 <DMA_ClearITPendingBit+0x34>
  {
    /* Set DMAy HIFCR register clear interrupt bits */
    DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
 8009722:	683b      	ldr	r3, [r7, #0]
 8009724:	4a0b      	ldr	r2, [pc, #44]	(8009754 <DMA_ClearITPendingBit+0x58>)
 8009726:	ea03 0202 	and.w	r2, r3, r2
 800972a:	68fb      	ldr	r3, [r7, #12]
 800972c:	60da      	str	r2, [r3, #12]
 800972e:	e005      	b.n	800973c <DMA_ClearITPendingBit+0x40>
  }
  else 
  {
    /* Set DMAy LIFCR register clear interrupt bits */
    DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
 8009730:	683b      	ldr	r3, [r7, #0]
 8009732:	4a08      	ldr	r2, [pc, #32]	(8009754 <DMA_ClearITPendingBit+0x58>)
 8009734:	ea03 0202 	and.w	r2, r3, r2
 8009738:	68fb      	ldr	r3, [r7, #12]
 800973a:	609a      	str	r2, [r3, #8]
  }   
}
 800973c:	f107 0714 	add.w	r7, r7, #20	; 0x14
 8009740:	46bd      	mov	sp, r7
 8009742:	bc80      	pop	{r7}
 8009744:	4770      	bx	lr
 8009746:	46c0      	nop			(mov r8, r8)
 8009748:	4002640f 	.word	0x4002640f
 800974c:	40026000 	.word	0x40026000
 8009750:	40026400 	.word	0x40026400
 8009754:	0f7d0f7d 	.word	0x0f7d0f7d

08009758 <EXTI_DeInit>:
  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
  * @param  None
  * @retval None
  */
void EXTI_DeInit(void)
{
 8009758:	b480      	push	{r7}
 800975a:	af00      	add	r7, sp, #0
  EXTI->IMR = 0x00000000;
 800975c:	4a0a      	ldr	r2, [pc, #40]	(8009788 <EXTI_DeInit+0x30>)
 800975e:	f04f 0300 	mov.w	r3, #0	; 0x0
 8009762:	6013      	str	r3, [r2, #0]
  EXTI->EMR = 0x00000000;
 8009764:	4a08      	ldr	r2, [pc, #32]	(8009788 <EXTI_DeInit+0x30>)
 8009766:	f04f 0300 	mov.w	r3, #0	; 0x0
 800976a:	6053      	str	r3, [r2, #4]
  EXTI->RTSR = 0x00000000;
 800976c:	4a06      	ldr	r2, [pc, #24]	(8009788 <EXTI_DeInit+0x30>)
 800976e:	f04f 0300 	mov.w	r3, #0	; 0x0
 8009772:	6093      	str	r3, [r2, #8]
  EXTI->FTSR = 0x00000000;
 8009774:	4a04      	ldr	r2, [pc, #16]	(8009788 <EXTI_DeInit+0x30>)
 8009776:	f04f 0300 	mov.w	r3, #0	; 0x0
 800977a:	60d3      	str	r3, [r2, #12]
  EXTI->PR = 0x007FFFFF;
 800977c:	4a02      	ldr	r2, [pc, #8]	(8009788 <EXTI_DeInit+0x30>)
 800977e:	4b03      	ldr	r3, [pc, #12]	(800978c <EXTI_DeInit+0x34>)
 8009780:	6153      	str	r3, [r2, #20]
}
 8009782:	46bd      	mov	sp, r7
 8009784:	bc80      	pop	{r7}
 8009786:	4770      	bx	lr
 8009788:	40013c00 	.word	0x40013c00
 800978c:	007fffff 	.word	0x007fffff

08009790 <EXTI_Init>:
  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
  *         that contains the configuration information for the EXTI peripheral.
  * @retval None
  */
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
 8009790:	b480      	push	{r7}
 8009792:	b085      	sub	sp, #20
 8009794:	af00      	add	r7, sp, #0
 8009796:	6078      	str	r0, [r7, #4]
  uint32_t tmp = 0;
 8009798:	f04f 0300 	mov.w	r3, #0	; 0x0
 800979c:	60fb      	str	r3, [r7, #12]
  //assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
  //assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
  //assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
  //assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));

  tmp = (uint32_t)EXTI_BASE;
 800979e:	4b3b      	ldr	r3, [pc, #236]	(800988c <EXTI_Init+0xfc>)
 80097a0:	60fb      	str	r3, [r7, #12]
     
  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
 80097a2:	687b      	ldr	r3, [r7, #4]
 80097a4:	799b      	ldrb	r3, [r3, #6]
 80097a6:	2b00      	cmp	r3, #0
 80097a8:	d05b      	beq.n	8009862 <EXTI_Init+0xd2>
  {
    /* Clear EXTI line configuration */
    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
 80097aa:	4938      	ldr	r1, [pc, #224]	(800988c <EXTI_Init+0xfc>)
 80097ac:	4b37      	ldr	r3, [pc, #220]	(800988c <EXTI_Init+0xfc>)
 80097ae:	681a      	ldr	r2, [r3, #0]
 80097b0:	687b      	ldr	r3, [r7, #4]
 80097b2:	681b      	ldr	r3, [r3, #0]
 80097b4:	ea6f 0303 	mvn.w	r3, r3
 80097b8:	ea02 0303 	and.w	r3, r2, r3
 80097bc:	600b      	str	r3, [r1, #0]
    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
 80097be:	4933      	ldr	r1, [pc, #204]	(800988c <EXTI_Init+0xfc>)
 80097c0:	4b32      	ldr	r3, [pc, #200]	(800988c <EXTI_Init+0xfc>)
 80097c2:	685a      	ldr	r2, [r3, #4]
 80097c4:	687b      	ldr	r3, [r7, #4]
 80097c6:	681b      	ldr	r3, [r3, #0]
 80097c8:	ea6f 0303 	mvn.w	r3, r3
 80097cc:	ea02 0303 	and.w	r3, r2, r3
 80097d0:	604b      	str	r3, [r1, #4]
    
    tmp += EXTI_InitStruct->EXTI_Mode;
 80097d2:	687b      	ldr	r3, [r7, #4]
 80097d4:	791b      	ldrb	r3, [r3, #4]
 80097d6:	461a      	mov	r2, r3
 80097d8:	68fb      	ldr	r3, [r7, #12]
 80097da:	4413      	add	r3, r2
 80097dc:	60fb      	str	r3, [r7, #12]

    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
 80097de:	68f9      	ldr	r1, [r7, #12]
 80097e0:	68fb      	ldr	r3, [r7, #12]
 80097e2:	681a      	ldr	r2, [r3, #0]
 80097e4:	687b      	ldr	r3, [r7, #4]
 80097e6:	681b      	ldr	r3, [r3, #0]
 80097e8:	ea42 0303 	orr.w	r3, r2, r3
 80097ec:	600b      	str	r3, [r1, #0]

    /* Clear Rising Falling edge configuration */
    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
 80097ee:	4927      	ldr	r1, [pc, #156]	(800988c <EXTI_Init+0xfc>)
 80097f0:	4b26      	ldr	r3, [pc, #152]	(800988c <EXTI_Init+0xfc>)
 80097f2:	689a      	ldr	r2, [r3, #8]
 80097f4:	687b      	ldr	r3, [r7, #4]
 80097f6:	681b      	ldr	r3, [r3, #0]
 80097f8:	ea6f 0303 	mvn.w	r3, r3
 80097fc:	ea02 0303 	and.w	r3, r2, r3
 8009800:	608b      	str	r3, [r1, #8]
    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
 8009802:	4922      	ldr	r1, [pc, #136]	(800988c <EXTI_Init+0xfc>)
 8009804:	4b21      	ldr	r3, [pc, #132]	(800988c <EXTI_Init+0xfc>)
 8009806:	68da      	ldr	r2, [r3, #12]
 8009808:	687b      	ldr	r3, [r7, #4]
 800980a:	681b      	ldr	r3, [r3, #0]
 800980c:	ea6f 0303 	mvn.w	r3, r3
 8009810:	ea02 0303 	and.w	r3, r2, r3
 8009814:	60cb      	str	r3, [r1, #12]
    
    /* Select the trigger for the selected external interrupts */
    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
 8009816:	687b      	ldr	r3, [r7, #4]
 8009818:	795b      	ldrb	r3, [r3, #5]
 800981a:	2b10      	cmp	r3, #16
 800981c:	d110      	bne.n	8009840 <EXTI_Init+0xb0>
    {
      /* Rising Falling edge */
      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
 800981e:	491b      	ldr	r1, [pc, #108]	(800988c <EXTI_Init+0xfc>)
 8009820:	4b1a      	ldr	r3, [pc, #104]	(800988c <EXTI_Init+0xfc>)
 8009822:	689a      	ldr	r2, [r3, #8]
 8009824:	687b      	ldr	r3, [r7, #4]
 8009826:	681b      	ldr	r3, [r3, #0]
 8009828:	ea42 0303 	orr.w	r3, r2, r3
 800982c:	608b      	str	r3, [r1, #8]
      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
 800982e:	4917      	ldr	r1, [pc, #92]	(800988c <EXTI_Init+0xfc>)
 8009830:	4b16      	ldr	r3, [pc, #88]	(800988c <EXTI_Init+0xfc>)
 8009832:	68da      	ldr	r2, [r3, #12]
 8009834:	687b      	ldr	r3, [r7, #4]
 8009836:	681b      	ldr	r3, [r3, #0]
 8009838:	ea42 0303 	orr.w	r3, r2, r3
 800983c:	60cb      	str	r3, [r1, #12]
 800983e:	e020      	b.n	8009882 <EXTI_Init+0xf2>
    }
    else
    {
      tmp = (uint32_t)EXTI_BASE;
 8009840:	4b12      	ldr	r3, [pc, #72]	(800988c <EXTI_Init+0xfc>)
 8009842:	60fb      	str	r3, [r7, #12]
      tmp += EXTI_InitStruct->EXTI_Trigger;
 8009844:	687b      	ldr	r3, [r7, #4]
 8009846:	795b      	ldrb	r3, [r3, #5]
 8009848:	461a      	mov	r2, r3
 800984a:	68fb      	ldr	r3, [r7, #12]
 800984c:	4413      	add	r3, r2
 800984e:	60fb      	str	r3, [r7, #12]

      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
 8009850:	68f9      	ldr	r1, [r7, #12]
 8009852:	68fb      	ldr	r3, [r7, #12]
 8009854:	681a      	ldr	r2, [r3, #0]
 8009856:	687b      	ldr	r3, [r7, #4]
 8009858:	681b      	ldr	r3, [r3, #0]
 800985a:	ea42 0303 	orr.w	r3, r2, r3
 800985e:	600b      	str	r3, [r1, #0]
 8009860:	e00f      	b.n	8009882 <EXTI_Init+0xf2>
    }
  }
  else
  {
    tmp += EXTI_InitStruct->EXTI_Mode;
 8009862:	687b      	ldr	r3, [r7, #4]
 8009864:	791b      	ldrb	r3, [r3, #4]
 8009866:	461a      	mov	r2, r3
 8009868:	68fb      	ldr	r3, [r7, #12]
 800986a:	4413      	add	r3, r2
 800986c:	60fb      	str	r3, [r7, #12]

    /* Disable the selected external lines */
    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
 800986e:	68f9      	ldr	r1, [r7, #12]
 8009870:	68fb      	ldr	r3, [r7, #12]
 8009872:	681a      	ldr	r2, [r3, #0]
 8009874:	687b      	ldr	r3, [r7, #4]
 8009876:	681b      	ldr	r3, [r3, #0]
 8009878:	ea6f 0303 	mvn.w	r3, r3
 800987c:	ea02 0303 	and.w	r3, r2, r3
 8009880:	600b      	str	r3, [r1, #0]
  }
}
 8009882:	f107 0714 	add.w	r7, r7, #20	; 0x14
 8009886:	46bd      	mov	sp, r7
 8009888:	bc80      	pop	{r7}
 800988a:	4770      	bx	lr
 800988c:	40013c00 	.word	0x40013c00

08009890 <EXTI_StructInit>:
  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
  *         be initialized.
  * @retval None
  */
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
 8009890:	b480      	push	{r7}
 8009892:	b083      	sub	sp, #12
 8009894:	af00      	add	r7, sp, #0
 8009896:	6078      	str	r0, [r7, #4]
  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
 8009898:	687a      	ldr	r2, [r7, #4]
 800989a:	f04f 0300 	mov.w	r3, #0	; 0x0
 800989e:	6013      	str	r3, [r2, #0]
  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
 80098a0:	687a      	ldr	r2, [r7, #4]
 80098a2:	f04f 0300 	mov.w	r3, #0	; 0x0
 80098a6:	7113      	strb	r3, [r2, #4]
  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
 80098a8:	687a      	ldr	r2, [r7, #4]
 80098aa:	f04f 030c 	mov.w	r3, #12	; 0xc
 80098ae:	7153      	strb	r3, [r2, #5]
  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
 80098b0:	687a      	ldr	r2, [r7, #4]
 80098b2:	f04f 0300 	mov.w	r3, #0	; 0x0
 80098b6:	7193      	strb	r3, [r2, #6]
}
 80098b8:	f107 070c 	add.w	r7, r7, #12	; 0xc
 80098bc:	46bd      	mov	sp, r7
 80098be:	bc80      	pop	{r7}
 80098c0:	4770      	bx	lr
 80098c2:	46c0      	nop			(mov r8, r8)

080098c4 <EXTI_GenerateSWInterrupt>:
  *         will be generated.
  *         This parameter can be any combination of EXTI_Linex where x can be (0..22)
  * @retval None
  */
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{
 80098c4:	b480      	push	{r7}
 80098c6:	b083      	sub	sp, #12
 80098c8:	af00      	add	r7, sp, #0
 80098ca:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  //assert_param(IS_EXTI_LINE(EXTI_Line));
  
  EXTI->SWIER |= EXTI_Line;
 80098cc:	4905      	ldr	r1, [pc, #20]	(80098e4 <EXTI_GenerateSWInterrupt+0x20>)
 80098ce:	4b05      	ldr	r3, [pc, #20]	(80098e4 <EXTI_GenerateSWInterrupt+0x20>)
 80098d0:	691a      	ldr	r2, [r3, #16]
 80098d2:	687b      	ldr	r3, [r7, #4]
 80098d4:	ea42 0303 	orr.w	r3, r2, r3
 80098d8:	610b      	str	r3, [r1, #16]
}
 80098da:	f107 070c 	add.w	r7, r7, #12	; 0xc
 80098de:	46bd      	mov	sp, r7
 80098e0:	bc80      	pop	{r7}
 80098e2:	4770      	bx	lr
 80098e4:	40013c00 	.word	0x40013c00

080098e8 <EXTI_GetFlagStatus>:
  * @param  EXTI_Line: specifies the EXTI line flag to check.
  *          This parameter can be EXTI_Linex where x can be(0..22)
  * @retval The new state of EXTI_Line (SET or RESET).
  */
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{
 80098e8:	b480      	push	{r7}
 80098ea:	b085      	sub	sp, #20
 80098ec:	af00      	add	r7, sp, #0
 80098ee:	6078      	str	r0, [r7, #4]
  FlagStatus bitstatus = RESET;
 80098f0:	f04f 0300 	mov.w	r3, #0	; 0x0
 80098f4:	73fb      	strb	r3, [r7, #15]
  /* Check the parameters */
  //assert_param(IS_GET_EXTI_LINE(EXTI_Line));
  
  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
 80098f6:	4b0a      	ldr	r3, [pc, #40]	(8009920 <EXTI_GetFlagStatus+0x38>)
 80098f8:	695a      	ldr	r2, [r3, #20]
 80098fa:	687b      	ldr	r3, [r7, #4]
 80098fc:	ea02 0303 	and.w	r3, r2, r3
 8009900:	2b00      	cmp	r3, #0
 8009902:	d003      	beq.n	800990c <EXTI_GetFlagStatus+0x24>
  {
    bitstatus = SET;
 8009904:	f04f 0301 	mov.w	r3, #1	; 0x1
 8009908:	73fb      	strb	r3, [r7, #15]
 800990a:	e002      	b.n	8009912 <EXTI_GetFlagStatus+0x2a>
  }
  else
  {
    bitstatus = RESET;
 800990c:	f04f 0300 	mov.w	r3, #0	; 0x0
 8009910:	73fb      	strb	r3, [r7, #15]
  }
  return bitstatus;
 8009912:	7bfb      	ldrb	r3, [r7, #15]
}
 8009914:	4618      	mov	r0, r3
 8009916:	f107 0714 	add.w	r7, r7, #20	; 0x14
 800991a:	46bd      	mov	sp, r7
 800991c:	bc80      	pop	{r7}
 800991e:	4770      	bx	lr
 8009920:	40013c00 	.word	0x40013c00

08009924 <EXTI_ClearFlag>:
  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
  * @retval None
  */
void EXTI_ClearFlag(uint32_t EXTI_Line)
{
 8009924:	b480      	push	{r7}
 8009926:	b083      	sub	sp, #12
 8009928:	af00      	add	r7, sp, #0
 800992a:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  //assert_param(IS_EXTI_LINE(EXTI_Line));
  
  EXTI->PR = EXTI_Line;
 800992c:	4a03      	ldr	r2, [pc, #12]	(800993c <EXTI_ClearFlag+0x18>)
 800992e:	687b      	ldr	r3, [r7, #4]
 8009930:	6153      	str	r3, [r2, #20]
}
 8009932:	f107 070c 	add.w	r7, r7, #12	; 0xc
 8009936:	46bd      	mov	sp, r7
 8009938:	bc80      	pop	{r7}
 800993a:	4770      	bx	lr
 800993c:	40013c00 	.word	0x40013c00

08009940 <EXTI_GetITStatus>:
  * @param  EXTI_Line: specifies the EXTI line to check.
  *          This parameter can be EXTI_Linex where x can be(0..22)
  * @retval The new state of EXTI_Line (SET or RESET).
  */
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
 8009940:	b480      	push	{r7}
 8009942:	b085      	sub	sp, #20
 8009944:	af00      	add	r7, sp, #0
 8009946:	6078      	str	r0, [r7, #4]
  FlagStatus bitstatus = RESET;
 8009948:	f04f 0300 	mov.w	r3, #0	; 0x0
 800994c:	73fb      	strb	r3, [r7, #15]
  /* Check the parameters */
  //assert_param(IS_GET_EXTI_LINE(EXTI_Line));
  
  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
 800994e:	4b0a      	ldr	r3, [pc, #40]	(8009978 <EXTI_GetITStatus+0x38>)
 8009950:	695a      	ldr	r2, [r3, #20]
 8009952:	687b      	ldr	r3, [r7, #4]
 8009954:	ea02 0303 	and.w	r3, r2, r3
 8009958:	2b00      	cmp	r3, #0
 800995a:	d003      	beq.n	8009964 <EXTI_GetITStatus+0x24>
  {
    bitstatus = SET;
 800995c:	f04f 0301 	mov.w	r3, #1	; 0x1
 8009960:	73fb      	strb	r3, [r7, #15]
 8009962:	e002      	b.n	800996a <EXTI_GetITStatus+0x2a>
  }
  else
  {
    bitstatus = RESET;
 8009964:	f04f 0300 	mov.w	r3, #0	; 0x0
 8009968:	73fb      	strb	r3, [r7, #15]
  }
  return bitstatus;
 800996a:	7bfb      	ldrb	r3, [r7, #15]
  
}
 800996c:	4618      	mov	r0, r3
 800996e:	f107 0714 	add.w	r7, r7, #20	; 0x14
 8009972:	46bd      	mov	sp, r7
 8009974:	bc80      	pop	{r7}
 8009976:	4770      	bx	lr
 8009978:	40013c00 	.word	0x40013c00

0800997c <EXTI_ClearITPendingBit>:
  * @param  EXTI_Line: specifies the EXTI lines to clear.
  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
  * @retval None
  */
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{
 800997c:	b480      	push	{r7}
 800997e:	b083      	sub	sp, #12
 8009980:	af00      	add	r7, sp, #0
 8009982:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  //assert_param(IS_EXTI_LINE(EXTI_Line));
  
  EXTI->PR = EXTI_Line;
 8009984:	4a03      	ldr	r2, [pc, #12]	(8009994 <EXTI_ClearITPendingBit+0x18>)
 8009986:	687b      	ldr	r3, [r7, #4]
 8009988:	6153      	str	r3, [r2, #20]
}
 800998a:	f107 070c 	add.w	r7, r7, #12	; 0xc
 800998e:	46bd      	mov	sp, r7
 8009990:	bc80      	pop	{r7}
 8009992:	4770      	bx	lr
 8009994:	40013c00 	.word	0x40013c00

08009998 <GPIO_DeInit>:
  *                      x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
  *                      x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.  
  * @retval None
  */
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
 8009998:	b580      	push	{r7, lr}
 800999a:	b082      	sub	sp, #8
 800999c:	af00      	add	r7, sp, #0
 800999e:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  //assert_param(IS_GPIO_ALL_PERIPH(GPIOx));

  if (GPIOx == GPIOA)
 80099a0:	687a      	ldr	r2, [r7, #4]
 80099a2:	4b5e      	ldr	r3, [pc, #376]	(8009b1c <GPIO_DeInit+0x184>)
 80099a4:	429a      	cmp	r2, r3
 80099a6:	d10c      	bne.n	80099c2 <GPIO_DeInit+0x2a>
  {
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
 80099a8:	f04f 0001 	mov.w	r0, #1	; 0x1
 80099ac:	f04f 0101 	mov.w	r1, #1	; 0x1
 80099b0:	f000 ff84 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
 80099b4:	f04f 0001 	mov.w	r0, #1	; 0x1
 80099b8:	f04f 0100 	mov.w	r1, #0	; 0x0
 80099bc:	f000 ff7e 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
 80099c0:	e0a8      	b.n	8009b14 <GPIO_DeInit+0x17c>
  }
  else if (GPIOx == GPIOB)
 80099c2:	687a      	ldr	r2, [r7, #4]
 80099c4:	4b56      	ldr	r3, [pc, #344]	(8009b20 <GPIO_DeInit+0x188>)
 80099c6:	429a      	cmp	r2, r3
 80099c8:	d10c      	bne.n	80099e4 <GPIO_DeInit+0x4c>
  {
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
 80099ca:	f04f 0002 	mov.w	r0, #2	; 0x2
 80099ce:	f04f 0101 	mov.w	r1, #1	; 0x1
 80099d2:	f000 ff73 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
 80099d6:	f04f 0002 	mov.w	r0, #2	; 0x2
 80099da:	f04f 0100 	mov.w	r1, #0	; 0x0
 80099de:	f000 ff6d 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
 80099e2:	e097      	b.n	8009b14 <GPIO_DeInit+0x17c>
  }
  else if (GPIOx == GPIOC)
 80099e4:	687a      	ldr	r2, [r7, #4]
 80099e6:	4b4f      	ldr	r3, [pc, #316]	(8009b24 <GPIO_DeInit+0x18c>)
 80099e8:	429a      	cmp	r2, r3
 80099ea:	d10c      	bne.n	8009a06 <GPIO_DeInit+0x6e>
  {
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
 80099ec:	f04f 0004 	mov.w	r0, #4	; 0x4
 80099f0:	f04f 0101 	mov.w	r1, #1	; 0x1
 80099f4:	f000 ff62 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
 80099f8:	f04f 0004 	mov.w	r0, #4	; 0x4
 80099fc:	f04f 0100 	mov.w	r1, #0	; 0x0
 8009a00:	f000 ff5c 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
 8009a04:	e086      	b.n	8009b14 <GPIO_DeInit+0x17c>
  }
  else if (GPIOx == GPIOD)
 8009a06:	687a      	ldr	r2, [r7, #4]
 8009a08:	4b47      	ldr	r3, [pc, #284]	(8009b28 <GPIO_DeInit+0x190>)
 8009a0a:	429a      	cmp	r2, r3
 8009a0c:	d10c      	bne.n	8009a28 <GPIO_DeInit+0x90>
  {
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
 8009a0e:	f04f 0008 	mov.w	r0, #8	; 0x8
 8009a12:	f04f 0101 	mov.w	r1, #1	; 0x1
 8009a16:	f000 ff51 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
 8009a1a:	f04f 0008 	mov.w	r0, #8	; 0x8
 8009a1e:	f04f 0100 	mov.w	r1, #0	; 0x0
 8009a22:	f000 ff4b 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
 8009a26:	e075      	b.n	8009b14 <GPIO_DeInit+0x17c>
  }
  else if (GPIOx == GPIOE)
 8009a28:	687a      	ldr	r2, [r7, #4]
 8009a2a:	4b40      	ldr	r3, [pc, #256]	(8009b2c <GPIO_DeInit+0x194>)
 8009a2c:	429a      	cmp	r2, r3
 8009a2e:	d10c      	bne.n	8009a4a <GPIO_DeInit+0xb2>
  {
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
 8009a30:	f04f 0010 	mov.w	r0, #16	; 0x10
 8009a34:	f04f 0101 	mov.w	r1, #1	; 0x1
 8009a38:	f000 ff40 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
 8009a3c:	f04f 0010 	mov.w	r0, #16	; 0x10
 8009a40:	f04f 0100 	mov.w	r1, #0	; 0x0
 8009a44:	f000 ff3a 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
 8009a48:	e064      	b.n	8009b14 <GPIO_DeInit+0x17c>
  }
  else if (GPIOx == GPIOF)
 8009a4a:	687a      	ldr	r2, [r7, #4]
 8009a4c:	4b38      	ldr	r3, [pc, #224]	(8009b30 <GPIO_DeInit+0x198>)
 8009a4e:	429a      	cmp	r2, r3
 8009a50:	d10c      	bne.n	8009a6c <GPIO_DeInit+0xd4>
  {
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
 8009a52:	f04f 0020 	mov.w	r0, #32	; 0x20
 8009a56:	f04f 0101 	mov.w	r1, #1	; 0x1
 8009a5a:	f000 ff2f 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
 8009a5e:	f04f 0020 	mov.w	r0, #32	; 0x20
 8009a62:	f04f 0100 	mov.w	r1, #0	; 0x0
 8009a66:	f000 ff29 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
 8009a6a:	e053      	b.n	8009b14 <GPIO_DeInit+0x17c>
  }
  else if (GPIOx == GPIOG)
 8009a6c:	687a      	ldr	r2, [r7, #4]
 8009a6e:	4b31      	ldr	r3, [pc, #196]	(8009b34 <GPIO_DeInit+0x19c>)
 8009a70:	429a      	cmp	r2, r3
 8009a72:	d10c      	bne.n	8009a8e <GPIO_DeInit+0xf6>
  {
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
 8009a74:	f04f 0040 	mov.w	r0, #64	; 0x40
 8009a78:	f04f 0101 	mov.w	r1, #1	; 0x1
 8009a7c:	f000 ff1e 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
 8009a80:	f04f 0040 	mov.w	r0, #64	; 0x40
 8009a84:	f04f 0100 	mov.w	r1, #0	; 0x0
 8009a88:	f000 ff18 	bl	800a8bc <RCC_AHB1PeriphResetCmd>
 8009a8c:	e042      	b.n	8009b14 <GPIO_DeInit+0x17c>
  }
  else if (GPIOx == GPIOH)