arch/arm/src/lpc54xx: The basic SPI driver is code complete but still...

arch/arm/src/lpc54xx:  The basic SPI driver is code complete but still untested.  This driver is 'basic' in that in only supports polled mode operations.

arch/arm/src/lpc54xx/Kconfig

@@ -667,6 +667,24 @@ endif # LPC54_EMC_DYNAMIC
 
 endmenu # EMC Configuration
 
+menu "SPI Master configuration"
+	depends on LPC54_HAVE_SPI_MASTER
+
+config LPC54_SPI_WIDEDATA
+	bool "Enable wide data"
+	default n
+	---help---
+		The LPC54xxx SPI supports data widths from 4 through 16 bits.  For
+		data from 4 through 8 bits; the receive and transmit data is
+		represented with a uint8_t type.  For the wider data, data is
+		represented with a uint16_t.  There is duplication of logic for this
+		different widths.   By default, SPI wide data is disabled since that
+		is the less frequently used data type and disabling wide data can
+		result in some size reduction.  Select this option if you need wide
+		SPI data.
+
+endmenu # SPI Master configuration
+
 menu "Ethernet configuration"
 	depends on LPC54_ETHERNET
 

arch/arm/src/lpc54xx/chip/lpc54_spi.h

@@ -288,11 +288,18 @@
 #  define SPI_DLY_TRANSFER_DELAY(n)   ((uint32_t)(n) << SPI_DLY_TRANSFER_DELAY_SHIFT)
 
 /* SPI Status register */
-#define SPI_STAT_
-/* SPI Interrupt Enable read and set */
-#define SPI_INTENSET_
-/* SPI Interrupt Enable Clear */
-#define SPI_INTENCLR_
+
+#define SPI_STAT_SSA                  (1 << 4)  /* Bit 4:  Slave Select Assert */
+#define SPI_STAT_SSD                  (1 << 5)  /* Bit 5:  Slave Select Deassert */
+#define SPI_STAT_STALLED              (1 << 6)  /* Bit 6:  Stalled status flag */
+#define SPI_STAT_ENDTRANSFER          (1 << 7)  /* Bit 7:  End Transfer control bit */
+#define SPI_STAT_MSTIDLE              (1 << 8)  /* Bit 8:  Master idle status flag */
+
+/* SPI Interrupt Enable read and set, SPI Interrupt Enable Clear, and SPI Interrupt Status */
+
+#define SPI_INT_SSA                   (1 << 4)  /* Bit 4:  Slave select assert interrupt */
+#define SPI_INT_SSD                   (1 << 5)  /* Bit 5:  Slave select deassert interrupt */
+#define SPI_INT_MSTIDLE               (1 << 8)  /* Bit 8:  Master idle interrupt */
 
 /* SPI clock Divider */
 
@@ -300,9 +307,6 @@
 #define SPI_DIV_MASK                  (0xffff << SPI_DIV_SHIFT)
 #  define SPI_DIV(n)                  ((uint32_t)((n)-1) << SPI_DIV_SHIFT)
 
-/* SPI Interrupt Status */
-#define SPI_INTSTAT_
-
 /* FIFO configuration and enable register */
 
 #define SPI_FIFOCFG_ENABLETX          (1 << 0)  /* Bit 0:  Enable the transmit FIFO) */
@@ -318,12 +322,23 @@
 #define SPI_FIFOCFG_EMPTYRX           (1 << 17) /* Bit 17: Empty command for the receive FIFO) */
 
 /* FIFO status register */
-#define SPI_FIFOSTAT_
+
+#define SPI_FIFOSTAT_TXERR            (1 << 0)  /* Bit 0:  TX FIFO error */
+#define SPI_FIFOSTAT_RXERR            (1 << 1)  /* Bit 1:  RX FIFO error */
+#define SPI_FIFOSTAT_PERINT           (1 << 3)  /* Bit 3:  Peripheral interrupt */
+#define SPI_FIFOSTAT_TXEMPTY          (1 << 4)  /* Bit 4:  Transmit FIFO empty */
+#define SPI_FIFOSTAT_TXNOTFULL        (1 << 5)  /* Bit 5:  Transmit FIFO not full */
+#define SPI_FIFOSTAT_RXNOTEMPTY       (1 << 6)  /* Bit 6:  Receive FIFO not empty */
+#define SPI_FIFOSTAT_RXFULL           (1 << 7)  /* Bit 7:  Receive FIFO full */
+#define SPI_FIFOSTAT_TXLVL_SHIFT      (8)       /* Bits 8-12:  Transmit FIFO current level */
+#define SPI_FIFOSTAT_TXLVL_MASK       (31 << SPI_FIFOSTAT_TXLVL_SHIFT)
+#define SPI_FIFOSTAT_RXLVL_SHIFT      (16)      /* Bits 16-20: Receive FIFO current level */
+#define SPI_FIFOSTAT_RXLVL_MASK       (31 << SPI_FIFOSTAT_RXLVL_SHIFT)
 
 /* FIFO trigger level settings for interrupt and DMA request */
 
-#define SPI_FIFOTRIG_TXLVLENA         (1 << 0)  /* Bit 0  Transmit FIFO level trigger enable */
-#define SPI_FIFOTRIG_RXLVLENA         (1 << 1)  /* Bit 1  Receive FIFO level trigger enable */
+#define SPI_FIFOTRIG_TXLVLENA         (1 << 0)  /* Bit 0:  Transmit FIFO level trigger enable */
+#define SPI_FIFOTRIG_RXLVLENA         (1 << 1)  /* Bit 1:  Receive FIFO level trigger enable */
 #define SPI_FIFOTRIG_TXLVL_SHIFT      (8)       /* Bits 8-11: Transmit FIFO level trigger point */
 #define SPI_FIFOTRIG_TXLVL_MASK       (15 << SPI_FIFOTRIG_TXLVL_SHIFT)
 #  define SPI_FIFOTRIG_TXLVL(n)       ((uint32_t)(n) << SPI_FIFOTRIG_TXLVL_SHIFT)
@@ -335,22 +350,28 @@
 #  define SPI_FIFOTRIG_RXLVL_NOTEMPTY (0 << SPI_FIFOTRIG_RXLVL_SHIFT)
 #  define SPI_FIFOTRIG_RXLVL_FULL     (7 << SPI_FIFOTRIG_RXLVL_SHIFT)
 
-/* FIFO interrupt enable set (enable) and read register */
-#define SPI_FIFOINTENSET_
-/* FIFO interrupt enable clear (disable) and read register */
-#define SPI_FIFOINTENCLR_
-/* FIFO interrupt status register */
-#define SPI_FIFOINTSTAT_
+/* FIFO interrupt enable set (enable) and read register, FIFO interrupt enable clear (disable)
+ * and read register, and FIFO interrupt status register
+ */
+
+#define SPI_FIFOINT_TXERR             (1 << 0)  /* Bit 0:  Transmit error interrupt */
+#define SPI_FIFOINT_RXERR             (1 << 1)  /* Bit 1:  Receive error interrupt */
+#define SPI_FIFOINT_TXLVL             (1 << 2)  /* Bit 2:  Tx FIFO level reached interrupt */
+#define SPI_FIFOINT_RXLVL             (1 << 3)  /* Bit 3:  Rx FIFO level reached interrupt */
+#define SPI_FIFOINTSTAT_PERINT        (1 << 4)  /* Bit 4:  Peripheral interrupt (status only) */
 
 /* FIFO write data */
 
 #define SPI_FIFOWR_TXDATA_SHIFT       (0)       /* Bits 0-15: Transmit data to the FIFO */
 #define SPI_FIFOWR_TXDATA_MASK        (0xffff << SPI_FIFOWR_TXDATA_SHIFT)
 #  define SPI_FIFOWR_TXDATA(n)        ((uint32_t)(n) << SPI_FIFOWR_TXDATA_SHIFT)
-#define SPI_FIFOWR_TXSSEL0_N          (1 << 16) /* Bit 16: Transmit Slave Select */
-#define SPI_FIFOWR_TXSSEL1_N          (1 << 17) /* Bit 17: Transmit Slave Select */
-#define SPI_FIFOWR_TXSSEL2_N          (1 << 18) /* Bit 18: Transmit Slave Select */
-#define SPI_FIFOWR_TXSSEL3_N          (1 << 19) /* Bit 19: Transmit Slave Select */
+#define SPI_FIFOWR_TXSSELN_SHIFT      (16)      /* Bits 16-19: Transmit Slave Selects */
+#define SPI_FIFOWR_TXSSELN_MASK       (15 << SPI_FIFOWR_TXSSELN_SHIFT)
+#  define SPI_FIFOWR_TXSSELN_ALL      (15 << SPI_FIFOWR_TXSSELN_SHIFT)
+#  define SPI_FIFOWR_TXSSEL0N         (1 << 16) /* Bit 16: Transmit Slave Select */
+#  define SPI_FIFOWR_TXSSEL1N         (1 << 17) /* Bit 17: Transmit Slave Select */
+#  define SPI_FIFOWR_TXSSEL2N         (1 << 18) /* Bit 18: Transmit Slave Select */
+#  define SPI_FIFOWR_TXSSEL3N         (1 << 19) /* Bit 19: Transmit Slave Select */
 #define SPI_FIFOWR_EOT                (1 << 20) /* Bit 20: End of Transfer */
 #define SPI_FIFOWR_EOF                (1 << 21) /* Bit 21: End of Frame */
 #define SPI_FIFOWR_RXIGNORE           (1 << 22) /* Bit 22: Receive Ignore */
@@ -358,11 +379,27 @@
 #define SPI_FIFOWR_LEN_MASK           (15 << SPI_FIFOWR_LEN_SHIFT)
 #  define SPI_FIFOWR_LEN(n)           ((uint32_t)((n)-1) << SPI_FIFOWR_LEN_SHIFT)
 
-/* FIFO read data */
-#define SPI_FIFORD_
-/* FIFO data read with no FIFO pop */
-#define SPI_FIFORDNOPOP_
+/* FIFO read data and FIFO data read with no FIFO pop */
+
+#define SPI_FIFORD_RXDATA_SHIFT       (0)       /* Bits 0-15:  Received data from the FIFO */
+#define SPI_FIFORD_RXDATA_MASK        (0xffff << SPI_FIFORD_RXDATA_SHIFT)
+#define SPI_FIFORD_RXSSELN_SHIFT      (16)      /* Bits 16-19:  Slave Selects for receive */
+#define SPI_FIFORD_RXSSELN_MASK       (15 << SPI_FIFORD_RXSSELN_SHIFT)
+#  define SPI_FIFORD_RXSSEL0N         (1 << 16) /* Bit 16: Slave Select for receive */
+#  define SPI_FIFORD_RXSSEL1N         (1 << 17) /* Bit 17: Slave Select for receive */
+#  define SPI_FIFORD_RXSSEL2N         (1 << 18) /* Bit 18: Slave Select for receive */
+#  define SPI_FIFORD_RXSSEL3N         (1 << 19) /* Bit 19: Slave Select for receive */
+#define SPI_FIFORD_SOT                (1 << 20) /* Bit 20: Start of Transfer flag */
+
 /* SPI module Identification */
-#define SPI_ID_
+
+#define SPI_ID_APERTURE_SHIFT         (0)       /* Bits 0-7:   Aperture encoded as (aperture size/4K) -1 */
+#define SPI_ID_APERTURE_MASK          (0xff << SPI_ID_APERTURE_SHIFT)
+#define SPI_ID_MINORREV_SHIFT         (8)       /* Bits 8-11:  Minor revision of module implementation */
+#define SPI_ID_MINORREV_MASK          (15 << SPI_ID_MINORREV_SHIFT)
+#define SPI_ID_MAJORREV_SHIFT         (12)      /* Bits 12-15: Major revision of module implementation */
+#define SPI_ID_MAJORREV_MASK          (15 << SPI_ID_MAJORREV_SHIFT)
+#define SPI_ID_ID_SHIFT               (15)      /* Bits 16-31: Unique module identifier for this IP block */
+#define SPI_ID_ID_MASK                (0xffff << SPI_ID_ID_SHIFT)
 
 #endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H */

arch/arm/src/lpc54xx/lpc54_spi_master.h

@@ -263,7 +263,7 @@ int lpc54_spi8_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, v
 #ifdef CONFIG_LPC54_SPI9_MASTER
 int lpc54_spi9_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
 #endif
-#endif
+#endif /* CONFIG_SPI_CALLBACK */
 
 #undef EXTERN
 #if defined(__cplusplus)

configs/lpcxpresso-lpc54628/README.txt

@@ -86,20 +86,13 @@ STATUS
     of this writing.  Also added the netnsh configuration will, eventually,
     be used to test the Ethernet driver.
   2018-01-01:  There Ethernet driver appears to be fully functional although
-    more testing is certainly needed.  I believe that there is a memory
-    corruption issue in the current configuration that cause problems
-    occasionally.  For example, after a longer Telnet session, I sometimes
-    see the following DEBUGASSERT after exiting the session from the host:
+    more testing is certainly needed.
+  2018-01-14:  The basic SPI driver is code complete but still untested.  It
+    is "basic" in the sense that it supports only polled mode (no DMA).
 
-      up_assert: Assertion failed at file:mm_heap/mm_free.c line: 129
-
-    which is a clear indication heap corruption.  Increasing the size of some
-    stacks might correct this problem, but I have not yet experimented with
-    that.  I have not seen the problem in any other context.
-
-  There is still no support for the Accelerometer, SPIFI, or USB.  There is a
-  complete but not-yet-functional SD card.  There is a partial SPI driver,
-  but no on-board SPI devices to test it.
+  There is still no support for the Accelerometer, SPIFI, or USB.  There are
+  complete but not-yet-functional SD card and SPI drivers.  There are no
+  on-board devices to support SPI testing.
 
 Configurations
 ==============

include/nuttx/spi/spi.h

@@ -70,8 +70,8 @@
  * Name: SPI_LOCK
  *
  * Description:
- *   On SPI busses where there are multiple devices, it will be necessary to
- *   lock SPI to have exclusive access to the busses for a sequence of
+ *   On SPI buses where there are multiple devices, it will be necessary to
+ *   lock SPI to have exclusive access to the buses for a sequence of
  *   transfers.  The bus should be locked before the chip is selected. After
  *   locking the SPI bus, the caller should then also call the setfrequency,
  *   setbits, and setmode methods to make sure that the SPI is properly